SystemVerilog allows a variable to be used as a variable OR
as an unresolved wire. The detection of this case was checking
the references to the affected value, instead of the l-value
references.
(cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)
This patch changes the method used to signal that a constant expression
is being elaborated from flags stored in global variables to flags
passed down the call chain. It also generates more informative error
messages when variable references are found in a constant expression.
During elaboration, it is sometimes efficient to collapse a
collections of PV drivers to a net to a single concatenation.
This removes a bunch of resolutions and other nodes, and also
is the only way that 2-value logic should work.
Currently the compiler coerces input ports to inout ports whenever
there is an internal driver connected to the internal port net.
This generates an error if the port is externally connected to
something other than a structural net. This patch modifies the
compiler to ensure port coercion only occurs in valid cases.
This patch adds some preliminary module port information to the ivl
interface. This may change as I investigate exactly what is needed.
It also fixes a few minor bugs (a missed local variable and spacing)
This patch removes the code that was deleting the signals in an L-value
concat if the concatenation failed to elaborate. This is incorrect since
the signal could be used in another context that is processed later. The
error message when an output/inout port fails to elaborate was also
improved to give the expression that is connected to the port.
The original message talks about an unresolved net which may be
something different/more encompassing. This patch explicitly adds
uwire to the message to make it clear to the user that a uwire
could cause this message.
I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
Operands to reduction unary operators are self determined, so
evaluate the operands that way. But this means that binary expressions
in this context should take pains to use their test_width tested
expression width.
This exposed a case where the test_width methods were not called
for self-determined expressions. Fix that too.
Creation of implicit nets requires knowledge of whether an identifier
has been declared before it is used. Currently implicit nets are
created during elaboration, but by this stage the order of declaration
and use is not known. This patch moves the creation of implicit nets
into the parser stage.
This patch is a major rewrite of the indexed part selects (+: and -:).
It made the following enhancements:
1. Make indexed part selects work correctly with both big and little
endian vectors.
2. Add a warning flag that warns about constant out of bounds/or 'bx
indexed selects.
3. Moved the -: parameter code to its own routine.
4. Added support for straddling before part selects in a CA.
5. Added more assert(! number_is_unknown) statements.
6. Add warning for &PV<> select with a signed index signal that is
less than the width of an int. This will be fixed later.
7. Add support for loading a 'bx/'bz constant into a numeric register.
8. Add a number of signed value fixes to the compiler/code generator.
9. Major fix of draw_select_expr() in the code generator.
Previously Icarus only supported a default net type of wire or none.
This patch adds the rest of the supported net types (all except
uwire and trireg) to the `default_nettype directive. It also fixes
make_implicit_net_() to use the default_nettype instead of always
using implicit (the same as wire).
In 1364-2005 it is an explicit error to take the select of a scalar
or real value. We added the checks for real a while ago. This patch
adds the functionality for scalar values. In the future we may want
to push the scalar property to the run time.
Part selects need to be fully defined. If not, then the resulting
expression is 'bx no matter what. The same for bit selects, when
the bit select expression is constant.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.
This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.
This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
If a part select (either a constant or constant indexed part select)
of a L-value is fully outside the signal the part select will be
omitted after printing a warning. If a part select straddles the
upper portion of a signal a warning will be printed. The run time
will use only the appropriate part of the select. Straddling the
lower part of the signal is not currently supported and a message
is printed for this case.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
Nothing to do with tab width! Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings. No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.
Low priority, simple entropy reduction. Please apply
unless it deletes some steganographic content you want
to keep.
In preparation for using the synthesize method to replace the
elaborate_net method of PExpr, rework the interface to the
synthesize() method. This changes no fnctionality, but does set
up the infrastructure for the next step.
Contribution statements have an l-value and r-value. Parse those
expressions into pform so that elaboration has something to work with.
In this process, this patch also changes the PECallFunction class to
use the vector template instead of the svector template. The latter
doesn't add anything over the STL vector template, so this is a start
of working the svector out.
This handles the general case of a non-real operand to a real-valued
division. This can turn up if only 1 operand of a divide is real. In
this case the division as a whole is real and the other operand must
be cast to real.
This method creates an extra node, but it should be a very compact
node and this node does no evaluation tricks so in the run time should
be no more expensive then folding the cast into the .arith/div.r itself.
Stephen Williams
Cary R
Martin Whitaker
Larry Doolittle
Martin Whitaker