Creation of implicit nets requires knowledge of whether an identifier
has been declared before it is used. Currently implicit nets are
created during elaboration, but by this stage the order of declaration
and use is not known. This patch moves the creation of implicit nets
into the parser stage.
This patch adds genvars to the elaboration process. It adds checks
that a genvar is defined for a generate loop and that a genvar does
not conflict with any other items in its name space.
In 1364-2005 it is an explicit error to take the select of a scalar
or real value. We added the checks for real a while ago. This patch
adds the functionality for scalar values. In the future we may want
to push the scalar property to the run time.
When a pin array is virtual, dll_target::signal() doesn't need
to make a corresponding set of stub nexa.
This patch includes new detection of oversized arrays, configurable
with the ARRAY_SIZE_LIMIT flag. This limit only applies to devirtualized
arrays; virtual arrays are only limited by your architecture's
unsigned int type.
The concept and earlier versions of this patch have been successfully
stress-tested by multiple people. This one causes no testsuite
regressions on my machine.
Closes: pr2023076
This patch adds messages in various places to warn that constant
user functions are not supported. It uses a global variable to
indicate when we are in a constant context. This is a bit of a
kludge, but works well without needing to change a bunch of code.
It is interesting to note that ports are elaborated late enough
that if we had the constant function evaluation code they would
evaluate correctly. This also applies to the function return
range, the concatenation repeat, specparams and initial values.
Signal definitions are early enough that elaboration is what is
failing because the function body is not available (has not been
elaborated). The same thing applies to both parameters and
localparms.
Verilog generate schemes support a special case where conditional
generate schemes that contain only a nested conditional generate
scheme do not create a new scope. Instead, it relies on the nested
generate scheme to generate the scope.
unary expressions that have problems should not assert in the
test_width method. Instead, let the error propagate back and be
handled during expression elaboration. This found a few places
where expression widths/types weren't probed before elaboration.
Named blocks create scopes, and generated named blocks' scopes can
have signals declared in them. So the elaborate_sig for the generate
scheme needs to call the elaborate_sig for the processes as well as
the obvious gates and tasks/functions.
The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
Signals may have VMA disciplines attached. Make the attached discipline
visible through the ivl_target.h API. Also, re-arrange the internal
handling of the discipline structure so that we can expose disciplines
through the ivl_target C API without creating new structures. The
t-dll-api implementations of the discipline access functions can look
at the elaborated discipline structure directly. This is possible since
the discipline parse and elaboration are very simple.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.
This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.
This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
This patch removes all the checks for constant expressions performed
during the parsing phase, as these checks are (mostly) repeated during
elaboration. It adds the missing check in the elaboration phase (the
RHS of a register initialisation), and improves the error reporting
and error recovery in other checks.
This patch fixes pr2132552, which was caused by a fault in the parser
constant expression checking.
Nothing to do with tab width! Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings. No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.
Low priority, simple entropy reduction. Please apply
unless it deletes some steganographic content you want
to keep.
The NetBranch object is connected, but not like an object, so the
NetPins object base class is factored out from NetObj to handle the
connectivity, and the NetBranch class uses the NetPins to connect a
branch.
Also, account for the fact that nets with a discipline are by default
real-valued.
Generating task/function definitions involves getting the functions
to put themselves into the generate scheme instead of the module,
and getting elaboration to elaborate those definitions in the
generate scheme.
Named begin/end blocks burried within generate schemes need to be
elaborated. Handle this by remembering to elaborate_scope on the
statements within the generate scheme.
In the process, clean up/regularize some of the member names and
methods.
IEEE1364 has specific names for the various generations of Verilog that
are supported. Icarus Verilog should stick to those names for selection
the language feature set.
In the process, the extensions that were tied to the 2x generations
are pulled out out and given their own enable flags. The makes all the
feature control more regular and understandable.
Update the rules for parsing user function definitions to allow
Verilog-2001 ANSI style port declarations. In the process, also
unify with the user task port declaration so that the types don't
diverge. The rules are the same for both, with the extra constraint
that function ports must all be input. This latter rule is checked
later, during elaboration, so that the task/function pform code
can be shared, and better error messages can be generated.
During elaborate_sig, the code to detect implicit wires did not
properly account for the possibility that the name is that of an
explicitly declared parameter.
It is questionable, but probably legal, for expressions passed as
arguments to input ports of various kinds of gates to implicitly
declare nets. This patch allows the scan through different types
of expressions for implicit nets.
The elaborate_sig handling here does not test for the legality of
having a non-trivial expression as argument to a port. For example,
it is definitely NOT legal to have r-value expressions passed to
output or inout ports. But that will be checked for later when the
instance is elaborated for real.
If implicit nets are declared during elaboration, then the success
of binding during elaboration will depend on the order of the code
in the source file.
Normally processes are found in the lexical scope of a module, but
there are special cases where processes (other then task/function
definitions) are in other lexical scopes. The most likely case is
initilizations that are in the lexical scope where the assigned
variable is declared.
In the process, the behaviors list is kept in the base PScope class
instead of the Module or any other derived lexical scope class.
This patch converts a constant real index to an integer value when
defining an array. This can happen when using 2**8 which returns a
real value since the operands are signed.
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
Modules, functions and tasks are named scopes so derive them all
from the PScope base class. These items all take scoped items, so
the eventual plan is to move these items into PScope.
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
This would have never been a problem with the actual circuit generated.
The problem was that the assert was checking values that had never been
set. The constructor now explicitly sets these values to zero and while
I was at it I added a couple more asserts.
This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.
When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).
The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
Handle real valued expressions in vector declarations. Also clean
up the handling of vector declaration expressions.
Signed-off-by: Stephen Williams <steve@icarus.com>
Martin Whitaker
Cary R
Larry Doolittle
Stephen Williams
Martin Whitaker
steve