fbe42f13e2
Update tgt- directories with cppcheck suggested fixes
2021-01-02 13:31:26 -08:00
21b24c7725
Fix more compile warnings and a minor bug
2013-07-11 19:10:25 -07:00
dec0fa622c
Add CXX warning flag to tgt-pcb and tgt-vhdl and fix warnings
2013-07-11 17:40:57 -07:00
ec49f10e2d
Revert bad merge from vhdl branch
2010-10-02 11:02:27 -07:00
43f904f793
Add uwire support to VHDL backend
...
Implemented as std_ulogic which behaves almost identically.
2010-09-30 12:22:39 +01:00
8cbff6def0
Cleanup various style issues.
...
This patch cleans up some style issues: no need to check that a value
is defined before freeing or deleting it, use C++ style casts, make
sure to NULL terminate strncpy(), empty() is faster than size() for
size == 0 or size >= 0 checks, re-scope some variables, etc.
2010-04-13 21:29:15 -07:00
1d3ac6bc1f
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
553f3d77a9
Code for VHDL array type
2008-07-17 11:43:59 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
a0dbb1aa5d
Fix more bugs in part selects
2008-07-07 21:45:27 +01:00
050aa277ae
Make vhdl_element::emit a little more generic
2008-07-01 10:37:22 +01:00
d7bb5658f2
Translate IVL_ST_DELAYX statements
2008-06-19 12:16:19 +01:00
2fb57805ea
Use signed rather than std_logic_vector
...
Arithmetic operators now working correctly
2008-06-14 18:03:25 +01:00
919c1d695c
Adding binary +
2008-06-14 17:09:31 +01:00
0df3eabe26
Convert `if (foo) ..' to `if foo = '1' then ..'
2008-06-12 11:36:21 +01:00
7eb41304e6
Generate rising/falling edge detectors
2008-06-12 10:36:38 +01:00
120b5dc80e
Add constant integers
2008-06-09 12:46:55 +01:00
1d28b935e8
Split vhdl_element.cc into multiple files
2008-06-08 13:27:48 +01:00
Cary R
Stephen Williams
Nick Gasson