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iverilog/vhdlpp/entity_elaborate.cc

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Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
/*
Some cppcheck cleanup
2025-10-13 02:35:15 +02:00
* Copyright (c) 2011-2025 Stephen Williams (steve@icarus.com)
Elaborate VHDL entity port types/expressions. We need to elaborate expressions so that function calls in expressions (i.e. ranges) get bound to their proper scope. This binding is in turn used to emit package scopes. This is particularly interesting for ports of entities.
2013-06-08 00:47:14 +02:00
* Copyright CERN 2013 / Stephen Williams (steve@icarus.com)
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
updated FSF-address
2012-08-29 03:41:23 +02:00
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
*/
# include "entity.h"
# include "compiler.h"
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
# include "architec.h"
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
# include "vtype.h"
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
# include <iostream>
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
# include <typeinfo>
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
# include <fstream>
# include <iomanip>
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
# include <cstring>
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
# include <cassert>
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
using namespace std;
int elaborate_entities(void)
{
int errors = 0;
for (map<perm_string,Entity*>::iterator cur = design_entities.begin()
; cur != design_entities.end() ; ++cur) {
errors += cur->second->elaborate();
}
return errors;
}
int Entity::elaborate()
{
int errors = 0;
if (verbose_flag)
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
cerr << "Elaborate entity " << get_name() << "..." << endl;
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
Fix most of the cppcheck warnings in the vhdlpp directory. Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-29 02:07:49 +02:00
if (arch_.empty()) {
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
cerr << get_fileline() << ": error: "
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
<< "No architectures to choose from for entity " << get_name()
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
<< "." << endl;
return 1;
}
Save the type name if an InterfacePort object.
2011-01-06 17:12:55 +01:00
Soft treating of multiple architectures in VHDL In VHDL it is allowed to have multiple architectures per one entity. The proper architecture should be then chosen in a configuration block. Now, if many architectures will be found, then there will be a warning message printed. FIXME notes are added in order not to forget about changes to be done
2011-03-23 10:27:32 +01:00
/* FIXME: the architecture for the entity should be chosen in configuration
block (not yet implemented). Multiple architectures are allowed in general */
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
if (arch_.size() > 1) {
cerr << get_fileline() << ": sorry: "
Soft treating of multiple architectures in VHDL In VHDL it is allowed to have multiple architectures per one entity. The proper architecture should be then chosen in a configuration block. Now, if many architectures will be found, then there will be a warning message printed. FIXME notes are added in order not to forget about changes to be done
2011-03-23 10:27:32 +01:00
<< "Multiple architectures for an entity are not yet supported"
<< ". Architectures for entity " << get_name() << " are:" << endl;
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin()
; cur != arch_.end() ; ++cur) {
cerr << get_fileline() << ": : " << cur->first
<< " at " << cur->second->get_fileline() << endl;
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
}
Soft treating of multiple architectures in VHDL In VHDL it is allowed to have multiple architectures per one entity. The proper architecture should be then chosen in a configuration block. Now, if many architectures will be found, then there will be a warning message printed. FIXME notes are added in order not to forget about changes to be done
2011-03-23 10:27:32 +01:00
//errors += 1;
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
}
Soft treating of multiple architectures in VHDL In VHDL it is allowed to have multiple architectures per one entity. The proper architecture should be then chosen in a configuration block. Now, if many architectures will be found, then there will be a warning message printed. FIXME notes are added in order not to forget about changes to be done
2011-03-23 10:27:32 +01:00
/* FIXME: here we should look at configuration block */
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
bind_arch_ = arch_.begin()->second;
if (verbose_flag)
cerr << "For entity " << get_name()
<< ", choosing architecture " << bind_arch_->get_name()
<< "." << endl;
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
Elaborate expressions for entity generics.
2011-10-30 02:07:03 +02:00
errors += elaborate_generic_exprs_();
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
errors += elaborate_ports_();
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
errors += bind_arch_->elaborate(this);
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
return errors;
}
Elaborate expressions for entity generics.
2011-10-30 02:07:03 +02:00
int Entity::elaborate_generic_exprs_()
{
int errors = 0;
for (vector<InterfacePort*>::const_iterator cur = parms_.begin()
; cur != parms_.end() ; ++cur) {
InterfacePort*curp = *cur;
vhdlpp: Fixed crash on unassociated generics.
2015-03-06 19:30:02 +01:00
if(curp->expr)
curp->expr->elaborate_expr(this, 0, curp->type);
Elaborate expressions for entity generics.
2011-10-30 02:07:03 +02:00
}
return errors;
}
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
int Entity::elaborate_ports_(void)
{
int errors = 0;
Put off array bound evaluation / describe entity generics as parameters Entity generics are easily implemented as module parameters, so make it so. Give the parameters their default values from the generic declaration. Array bounds may use values that cannot be evaluated right away, so put off their evaluation.
2011-10-16 02:41:48 +02:00
for (std::vector<InterfacePort*>::const_iterator cur = ports_.begin()
; cur != ports_.end() ; ++cur) {
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
Some cppcheck cleanup
2025-10-13 02:35:15 +02:00
const InterfacePort*cur_port = *cur;
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
const VType*type = cur_port->type;
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
if (type == 0) {
cerr << get_fileline() << ": error: "
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
<< "Giving up on unknown type for port " << cur_port->name
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
<< "." << endl;
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
errors += 1;
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
continue;
}
Be more precide about mappings to Verilog types. Make std_logic map to Verilog logic, and integers and bits map to Verilog bool. These are more precise and accurate.
2011-02-05 04:30:40 +01:00
Elaborate VHDL entity port types/expressions. We need to elaborate expressions so that function calls in expressions (i.e. ranges) get bound to their proper scope. This binding is in turn used to emit package scopes. This is particularly interesting for ports of entities.
2013-06-08 00:47:14 +02:00
// Elaborate the type to elaborate any expressions that
// are used by the types.
errors += type->elaborate(this, bind_arch_);
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
VType::decl_t cur_decl;
cur_decl.type = type;
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
declarations_[cur_port->name] = cur_decl;
}
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
return errors;
}