luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/vhdlpp/entity_elaborate.cc

133 lines
3.5 KiB
C++
Raw Normal View History

Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "entity.h"
# include "compiler.h"
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
# include "architec.h"
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
# include "vtype.h"
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
# include <iostream>
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
# include <typeinfo>
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
# include <fstream>
# include <iomanip>
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
# include <cstring>
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
using namespace std;
int elaborate_entities(void)
{
int errors = 0;
for (map<perm_string,Entity*>::iterator cur = design_entities.begin()
; cur != design_entities.end() ; ++cur) {
errors += cur->second->elaborate();
}
return errors;
}
int Entity::elaborate()
{
int errors = 0;
if (verbose_flag)
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
cerr << "Elaborate entity " << name_ << "..." << endl;
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
if (arch_.size() == 0) {
cerr << get_fileline() << ": error: "
<< "No architectures to choose from for entity " << name_
<< "." << endl;
return 1;
}
Save the type name if an InterfacePort object.
2011-01-06 17:12:55 +01:00
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
if (arch_.size() > 1) {
cerr << get_fileline() << ": sorry: "
<< "Too many architectures for entity " << name_
<< ". Architectures are:" << endl;
for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin()
; cur != arch_.end() ; ++cur) {
cerr << get_fileline() << ": : " << cur->first
<< " at " << cur->second->get_fileline() << endl;
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
}
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
errors += 1;
}
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
bind_arch_ = arch_.begin()->second;
if (verbose_flag)
cerr << "For entity " << get_name()
<< ", choosing architecture " << bind_arch_->get_name()
<< "." << endl;
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
errors += elaborate_ports_();
return errors;
}
int Entity::elaborate_ports_(void)
{
int errors = 0;
for (std::vector<InterfacePort*>::const_iterator cur = ports_.begin()
; cur != ports_.end() ; ++cur) {
InterfacePort*cur_port = *cur;
decl_t cur_decl;
cur_decl.type = VNONE;
Be more precide about mappings to Verilog types. Make std_logic map to Verilog logic, and integers and bits map to Verilog bool. These are more precise and accurate.
2011-02-05 04:30:40 +01:00
cur_decl.signed_flag = false;
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
cur_decl.msb = 0;
cur_decl.lsb = 0;
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
const VType*type = cur_port->type;
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
if (type == 0) {
cerr << get_fileline() << ": error: "
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
<< "Giving up on unknown type for port " << cur_port->name
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
<< "." << endl;
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
errors += 1;
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
continue;
}
Be more precide about mappings to Verilog types. Make std_logic map to Verilog logic, and integers and bits map to Verilog bool. These are more precise and accurate.
2011-02-05 04:30:40 +01:00
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
if (const VTypePrimitive*use_type = dynamic_cast<const VTypePrimitive*>(type)) {
switch (use_type->type()) {
case VTypePrimitive::BOOLEAN:
case VTypePrimitive::BIT:
cur_decl.type = VBOOL;
break;
case VTypePrimitive::STDLOGIC:
cur_decl.type = VLOGIC;
break;
case VTypePrimitive::INTEGER:
cur_decl.type = VBOOL;
cur_decl.msb = 31;
cur_decl.lsb = 0;
break;
}
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
} else {
cerr << get_fileline() << ": error: "
<< "I don't know how to map port " << cur_port->name
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
<< " type " << typeid(*cur_port->type).name() << "." << endl;
Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.
2011-02-03 06:15:46 +01:00
errors += 1;
}
declarations_[cur_port->name] = cur_decl;
}
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
return errors;
}