iverilog/tgt-vhdl/vhdl_target.h

// -*- mode: c++ -*-
#ifndef INC_VHDL_TARGET_H
#define INC_VHDL_TARGET_H

#include "vhdl_config.h"
#include "ivl_target.h"

#include "support.hh"
#include "vhdl_syntax.hh"

#include <string>

void error(const char *fmt, ...);
void debug_msg(const char *fmt, ...);

int draw_scope(ivl_scope_t scope, void *_parent);
extern "C" int draw_process(ivl_process_t net, void *cd);
int draw_stmt(vhdl_procedural *proc, stmt_container *container,
              ivl_statement_t stmt, bool is_last = false);
int draw_lpm(vhdl_arch *arch, ivl_lpm_t lpm);
void draw_logic(vhdl_arch *arch, ivl_net_logic_t log);

vhdl_expr *translate_expr(ivl_expr_t e);
vhdl_expr *translate_time_expr(ivl_expr_t e);

ivl_design_t get_vhdl_design();
vhdl_var_ref *nexus_to_var_ref(vhdl_scope *arch_scope, ivl_nexus_t nexus);
vhdl_var_ref* readable_ref(vhdl_scope* scope, ivl_nexus_t nex);
std::string make_safe_name(ivl_signal_t sig);
void require_support_function(support_function_t f);

#endif /* #ifndef INC_VHDL_TARGET_H */
Generate VHDL report statements for $display This changes the implementation of $display/$write to use VHDL report statements rather the the std.textio functions. The code produced is simpler and more like what a real VHDL designed would write. However it no longer exactly matches the Verilog output as most VHDL simulators prepend the text with simulation time, entity name, severity level, etc. There is a corresponding change in ivtest to support this. Conflicts: tgt-vhdl/cast.cc tgt-vhdl/display.cc tgt-vhdl/vhdl_syntax.cc tgt-vhdl/vhdl_target.h 2010-10-05 21:02:04 +02:00			`// -- mode: c++ --`
Makefile and autoconf changes to build VHDL code generator 2008-05-28 18:17:39 +02:00			`#ifndef INC_VHDL_TARGET_H`
			`#define INC_VHDL_TARGET_H`

			`#include "vhdl_config.h"`
			`#include "ivl_target.h"`

Refactor support function code a bit 2008-07-19 21:49:55 +02:00			`#include "support.hh"`
Support named blocks with local variables in VHDL target This patch adds code to generate process-local variables for scopes of type IVL_SCT_BLOCK. This also handles using the correct assignment operator (:=) for the local VHDL variables. 2009-01-31 22:00:39 +01:00			`#include "vhdl_syntax.hh"`
Refactor support function code a bit 2008-07-19 21:49:55 +02:00
Generate VHDL processes from Verilog processes 2008-06-02 17:17:01 +02:00			`#include <string>`

Pretty-print VHDL output 2008-05-29 17:24:16 +02:00			`void error(const char *fmt, ...);`
Add debugging output to VHDL target Prints progress when -pdebug=1 specified. Adds a new debug_msg function to print progress messages. 2008-11-29 23:16:46 +01:00			`void debug_msg(const char *fmt, ...);`
Pretty-print VHDL output 2008-05-29 17:24:16 +02:00
Generate VHDL entities and architectures for all module scopes 2008-05-31 16:28:25 +02:00			`int draw_scope(ivl_scope_t scope, void *_parent);`
C++ functions passed to C should be declared extern "C" (second patch) The SunPro compiler was complaining about C++ routines that were being passed to the ivl C routines if the C++ routines were not declared extern "C". 2010-05-13 02:06:46 +02:00			`extern "C" int draw_process(ivl_process_t net, void *cd);`
Finish replacing vhdl_process with vhdl_procedural 2008-06-24 21:01:06 +02:00			`int draw_stmt(vhdl_procedural proc, stmt_container container,`
Avoid generating useless `wait for 0ns' statements If the final statement in a process is a non-blocking assignment then there is no point adding a `wait for 0ns' after it since it will be immediately followed by another wait. This case is suprisingly common, so this patch helps generate much cleaner output without breaking the cases where the 0ns wait is actually required (e.g. to implement non-blocking assignment properly). 2008-08-05 12:02:36 +02:00			`ivl_statement_t stmt, bool is_last = false);`
Minial LPM to support continuous assignments 2008-06-16 20:41:01 +02:00			`int draw_lpm(vhdl_arch *arch, ivl_lpm_t lpm);`
Split logic device code into separate file 2008-07-30 11:13:08 +02:00			`void draw_logic(vhdl_arch *arch, ivl_net_logic_t log);`
Generate VHDL entities and architectures for all module scopes 2008-05-31 16:28:25 +02:00
Stub code for translating expressions 2008-06-04 15:59:04 +02:00			`vhdl_expr *translate_expr(ivl_expr_t e);`
Refactor the expression->time code into a single function 2008-07-23 17:18:49 +02:00			`vhdl_expr *translate_time_expr(ivl_expr_t e);`
Stub code for translating expressions 2008-06-04 15:59:04 +02:00
Allow optional VHPI $finish implementation 2008-06-17 21:16:16 +02:00			`ivl_design_t get_vhdl_design();`
Refactor code to use the new vhdl_scope class 2008-06-24 19:52:25 +02:00			`vhdl_var_ref nexus_to_var_ref(vhdl_scope arch_scope, ivl_nexus_t nexus);`
Fix some more errors when reading from VHDL outputs I forgot to modify the LPM generating code with the last patch. This should now always ensure a signal is readable before code is generated to read from it. 2009-01-25 10:30:21 +01:00			`vhdl_var_ref* readable_ref(vhdl_scope* scope, ivl_nexus_t nex);`
Remove "using namespace std" from tgt-vhdl header files and fix the fallout. 2021-11-04 18:01:16 +01:00			`std::string make_safe_name(ivl_signal_t sig);`
Refactor support function code a bit 2008-07-19 21:49:55 +02:00			`void require_support_function(support_function_t f);`
Support functions for converting (un)signed -> boolean 2008-07-19 16:15:16 +02:00
Makefile and autoconf changes to build VHDL code generator 2008-05-28 18:17:39 +02:00			`#endif /* #ifndef INC_VHDL_TARGET_H */`