iverilog/tgt-vhdl/vhdl_target.h

#ifndef INC_VHDL_TARGET_H
#define INC_VHDL_TARGET_H

#include "vhdl_config.h"
#include "ivl_target.h"

#include "vhdl_element.hh"

#include <string>

void error(const char *fmt, ...);

int draw_scope(ivl_scope_t scope, void *_parent);
int draw_process(ivl_process_t net, void *cd);
int draw_stmt(vhdl_process *proc, ivl_statement_t stmt);

void remember_entity(vhdl_entity *ent);
vhdl_entity *find_entity(const std::string &tname);

#endif /* #ifndef INC_VHDL_TARGET_H */
Makefile and autoconf changes to build VHDL code generator 2008-05-28 18:17:39 +02:00			`#ifndef INC_VHDL_TARGET_H`
			`#define INC_VHDL_TARGET_H`

			`#include "vhdl_config.h"`
			`#include "ivl_target.h"`

Generate VHDL entities and architectures for all module scopes 2008-05-31 16:28:25 +02:00			`#include "vhdl_element.hh"`

Generate VHDL processes from Verilog processes 2008-06-02 17:17:01 +02:00			`#include <string>`

Pretty-print VHDL output 2008-05-29 17:24:16 +02:00			`void error(const char *fmt, ...);`

Generate VHDL entities and architectures for all module scopes 2008-05-31 16:28:25 +02:00			`int draw_scope(ivl_scope_t scope, void *_parent);`
			`int draw_process(ivl_process_t net, void *cd);`
Stub file for processing statements 2008-06-03 19:26:36 +02:00			`int draw_stmt(vhdl_process *proc, ivl_statement_t stmt);`
Generate VHDL entities and architectures for all module scopes 2008-05-31 16:28:25 +02:00
			`void remember_entity(vhdl_entity *ent);`
Generate VHDL processes from Verilog processes 2008-06-02 17:17:01 +02:00			`vhdl_entity *find_entity(const std::string &tname);`
Generate VHDL entities and architectures for all module scopes 2008-05-31 16:28:25 +02:00
Makefile and autoconf changes to build VHDL code generator 2008-05-28 18:17:39 +02:00			`#endif /* #ifndef INC_VHDL_TARGET_H */`