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iverilog/vhdlpp/expression_elaborate.cc

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Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
/*
Elaborate prefix names which may be structure variables.
2012-04-09 00:45:17 +02:00
* Copyright (c) 2011-2012 Stephen Williams (steve@icarus.com)
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
updated FSF-address
2012-08-29 03:41:23 +02:00
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
* Picture Elements, Inc., 777 Panoramic Way, Berkeley, CA 94704.
*/
# include "expression.h"
# include "architec.h"
# include "entity.h"
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
# include "vsignal.h"
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
# include <iostream>
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
# include <typeinfo>
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
# include "parse_types.h"
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
# include "ivl_assert.h"
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
using namespace std;
vhdl sequential l-values cause variables to be reg vs. net. When a signal (or port) is assigned by a sequential assignment, the signal or port becomes a reg, instead of a wire(net). Detect this distinction during elaboration and generate the correct signal/port declaration.
2011-06-13 00:38:03 +02:00
int Expression::elaborate_lval(Entity*, Architecture*, bool)
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
{
Put off array bound evaluation / describe entity generics as parameters Entity generics are easily implemented as module parameters, so make it so. Give the parameters their default values from the generic declaration. Array bounds may use values that cannot be evaluated right away, so put off their evaluation.
2011-10-16 02:41:48 +02:00
cerr << get_fileline() << ": error: Expression is not a valid l-value." << endl;
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
return 1;
}
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
const VType* Expression::probe_type(Entity*, Architecture*) const
{
return 0;
}
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
const VType* Expression::fit_type(Entity*ent, Architecture*arc, const VTypeArray*) const
{
const VType*res = probe_type(ent,arc);
if (res == 0) {
cerr << get_fileline() << ": internal error: "
<< "fit_type for " << typeid(*this).name()
<< " is not implemented." << endl;
}
return res;
}
Elaborate prefix names which may be structure variables.
2012-04-09 00:45:17 +02:00
const VType*ExpName::elaborate_adjust_type_with_range_(Entity*, Architecture*arc, const VType*type)
{
if (const VTypeArray*array = dynamic_cast<const VTypeArray*>(type)) {
if (index_ && !lsb_) {
// If the name is an array or a vector, then an
// indexed name has the type of the element.
type = array->element_type();
} else if (index_ && lsb_) {
// If the name is an array, then a part select is
// also an array, but with different bounds.
int64_t use_msb, use_lsb;
bool flag;
flag = index_->evaluate(arc, use_msb);
ivl_assert(*this, flag);
flag = lsb_->evaluate(arc, use_lsb);
ivl_assert(*this, flag);
Expression*exp_msb = new ExpInteger(use_msb);
Expression*exp_lsb = new ExpInteger(use_lsb);
vector<VTypeArray::range_t> use_dims (1);
use_dims[0] = VTypeArray::range_t(exp_msb, exp_lsb);
type = new VTypeArray(array->element_type(), use_dims);
}
}
return type;
}
int ExpName::elaborate_lval_(Entity*ent, Architecture*arc, bool is_sequ, ExpName*suffix)
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
{
int errors = 0;
Parse name prefix syntax for record member reference. When signals/variables are records, they are often referenced by their members, using a prefix.name syntax. Parse that syntax and generate "sorry" messages in elaboration.
2012-04-01 01:29:40 +02:00
if (prefix_.get()) {
cerr << get_fileline() << ": sorry: I don't know how to elaborate "
<< "ExpName prefix of " << name_
<< " in l-value expressions." << endl;
errors += 1;
}
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
const VType*found_type = 0;
Elaborate prefix names which may be structure variables.
2012-04-09 00:45:17 +02:00
if (const InterfacePort*cur = ent->find_port(name_)) {
if (cur->mode != PORT_OUT) {
cerr << get_fileline() << ": error: Assignment to "
"input port " << name_ << "." << endl;
return errors + 1;
}
if (is_sequ)
ent->set_declaration_l_value(name_, is_sequ);
found_type = cur->type;
} else if (ent->find_generic(name_)) {
cerr << get_fileline() << ": error: Assignment to generic "
<< name_ << " from entity "
<< ent->get_name() << "." << endl;
return errors + 1;
} else if (Signal*sig = arc->find_signal(name_)) {
// Tell the target signal that this may be a sequential l-value.
if (is_sequ) sig->count_ref_sequ();
found_type = sig->peek_type();
} else if (Variable*var = arc->find_variable(name_)) {
// Tell the target signal that this may be a sequential l-value.
if (is_sequ) var->count_ref_sequ();
found_type = var->peek_type();
}
ivl_assert(*this, found_type);
const VType*suffix_type = 0;
if (const VTypeRecord*record = dynamic_cast<const VTypeRecord*> (found_type)) {
const VTypeRecord::element_t*element = record->element_by_name(suffix->name_);
ivl_assert(*this, element);
const VType*element_type = element->peek_type();
ivl_assert(*this, element_type);
suffix_type = element_type;
}
if (suffix_type == 0) {
cerr << get_fileline() << ": error: I don't know how to handle prefix " << name_
<< " with suffix " << suffix->name_ << endl;
errors += 1;
return errors;
}
suffix_type = suffix->elaborate_adjust_type_with_range_(ent, arc, suffix_type);
ivl_assert(*this, suffix_type);
suffix->set_type(suffix_type);
return errors;
}
int ExpName::elaborate_lval(Entity*ent, Architecture*arc, bool is_sequ)
{
int errors = 0;
if (prefix_.get()) {
return prefix_->elaborate_lval_(ent, arc, is_sequ, this);
}
const VType*found_type = 0;
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
if (const InterfacePort*cur = ent->find_port(name_)) {
if (cur->mode != PORT_OUT) {
cerr << get_fileline() << ": error: Assignment to "
"input port " << name_ << "." << endl;
return errors += 1;
}
vhdl sequential l-values cause variables to be reg vs. net. When a signal (or port) is assigned by a sequential assignment, the signal or port becomes a reg, instead of a wire(net). Detect this distinction during elaboration and generate the correct signal/port declaration.
2011-06-13 00:38:03 +02:00
if (is_sequ)
ent->set_declaration_l_value(name_, is_sequ);
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
found_type = cur->type;
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
Put off array bound evaluation / describe entity generics as parameters Entity generics are easily implemented as module parameters, so make it so. Give the parameters their default values from the generic declaration. Array bounds may use values that cannot be evaluated right away, so put off their evaluation.
2011-10-16 02:41:48 +02:00
} else if (ent->find_generic(name_)) {
cerr << get_fileline() << ": error: Assignment to generic "
<< name_ << " from entity "
<< ent->get_name() << "." << endl;
return 1;
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
} else if (Signal*sig = arc->find_signal(name_)) {
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
// Tell the target signal that this may be a sequential l-value.
if (is_sequ) sig->count_ref_sequ();
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
found_type = sig->peek_type();
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
} else if (Variable*var = arc->find_variable(name_)) {
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
// Tell the target signal that this may be a sequential l-value.
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
if (is_sequ) var->count_ref_sequ();
found_type = var->peek_type();
}
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
if (found_type == 0) {
cerr << get_fileline() << ": error: Signal/variable " << name_
<< " not found in this context." << endl;
return errors + 1;
}
Elaborate prefix names which may be structure variables.
2012-04-09 00:45:17 +02:00
found_type = elaborate_adjust_type_with_range_(ent, arc, found_type);
vhdl sequential l-values cause variables to be reg vs. net. When a signal (or port) is assigned by a sequential assignment, the signal or port becomes a reg, instead of a wire(net). Detect this distinction during elaboration and generate the correct signal/port declaration.
2011-06-13 00:38:03 +02:00
Index/part select of VHDL l-values changes expression type The changed expression type impacts how code is generated for the r-value expression.
2011-09-04 02:57:37 +02:00
set_type(found_type);
return errors;
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
}
Add semantics check in component instantiation There have been applied rules for port and signal association in component instatiation statements described in the VHDL standard.
2011-07-12 18:09:50 +02:00
int ExpName::elaborate_rval(Entity*ent, Architecture*arc, const InterfacePort*lval)
Add ExpName::elaborate_rval member function This function is for the time being used in the component instatiation. It is checked, whether an expression is a correct r-value. To be a correct r-value, it must be either port name or signal name.
2011-07-20 06:29:05 +02:00
{
int errors = 0;
Parse name prefix syntax for record member reference. When signals/variables are records, they are often referenced by their members, using a prefix.name syntax. Parse that syntax and generate "sorry" messages in elaboration.
2012-04-01 01:29:40 +02:00
if (prefix_.get()) {
cerr << get_fileline() << ": sorry: I don't know how to elaborate "
<< "ExpName prefix parts in r-value expressions." << endl;
errors += 1;
}
Add ExpName::elaborate_rval member function This function is for the time being used in the component instatiation. It is checked, whether an expression is a correct r-value. To be a correct r-value, it must be either port name or signal name.
2011-07-20 06:29:05 +02:00
if (const InterfacePort*cur = ent->find_port(name_)) {
Add semantics check in component instantiation There have been applied rules for port and signal association in component instatiation statements described in the VHDL standard.
2011-07-12 18:09:50 +02:00
/* IEEE 1076-2008, p.80:
* For a formal port IN, associated port should be IN, OUT, INOUT or BUFFER
* For a formal port OUT, associated port should be OUT, INOUT or BUFFER
Spelling fixes to vhdlpp tree Mostly comments as usual, but one error message is changed.
2012-05-14 18:58:49 +02:00
* For a formal port INOUT, associated port should be OUT, INOUT or BUFFER
Add semantics check in component instantiation There have been applied rules for port and signal association in component instatiation statements described in the VHDL standard.
2011-07-12 18:09:50 +02:00
* For a formal port BUFFER, associated port should be OUT, INOUT or BUFFER
*/
switch(lval->mode) {
case PORT_OUT:
//case PORT_INOUT:
if (cur->mode == PORT_IN) {
cerr << get_fileline() << ": error: Connecting "
"formal output port " << lval->name << " to actual input port "
<< name_ << "." << endl;
errors += 1;
}
break;
case PORT_IN:
case PORT_NONE:
default:
break;
}
Remove all the user code compilation warnings Remove all the compilation warnings that are from user changeable code. There are still some warnings related to the flex generated lexor code.
2011-07-29 02:31:42 +02:00
} else if (arc->find_signal(name_)) {
Add ExpName::elaborate_rval member function This function is for the time being used in the component instatiation. It is checked, whether an expression is a correct r-value. To be a correct r-value, it must be either port name or signal name.
2011-07-20 06:29:05 +02:00
/* OK */
Handle arrays of vectors in VHDL types. This incidentally adds binding of generic to generic instantation.
2011-11-06 18:01:02 +01:00
} else if (ent->find_generic(name_)) {
/* OK */
Add ExpName::elaborate_rval member function This function is for the time being used in the component instatiation. It is checked, whether an expression is a correct r-value. To be a correct r-value, it must be either port name or signal name.
2011-07-20 06:29:05 +02:00
} else {
cerr << get_fileline() << ": error: No port or signal " << name_
<< " to be used as r-value." << endl;
errors += 1;
}
return errors;
}
vhdl sequential l-values cause variables to be reg vs. net. When a signal (or port) is assigned by a sequential assignment, the signal or port becomes a reg, instead of a wire(net). Detect this distinction during elaboration and generate the correct signal/port declaration.
2011-06-13 00:38:03 +02:00
int ExpNameALL::elaborate_lval(Entity*ent, Architecture*arc, bool is_sequ)
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
{
vhdl sequential l-values cause variables to be reg vs. net. When a signal (or port) is assigned by a sequential assignment, the signal or port becomes a reg, instead of a wire(net). Detect this distinction during elaboration and generate the correct signal/port declaration.
2011-06-13 00:38:03 +02:00
return Expression::elaborate_lval(ent, arc, is_sequ);
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
}
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
int Expression::elaborate_expr(Entity*, Architecture*, const VType*)
{
cerr << get_fileline() << ": internal error: I don't know how to elaborate expression type=" << typeid(*this).name() << endl;
return 1;
}
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
const VType* ExpBinary::probe_type(Entity*ent, Architecture*arc) const
{
const VType*t1 = operand1_->probe_type(ent, arc);
const VType*t2 = operand2_->probe_type(ent, arc);
if (t1 == 0)
return t2;
if (t2 == 0)
return t1;
if (t1 == t2)
return t1;
Properly elaborate argument types for binary relation expressions. The argument types of binary relation expressions are decoupled from the return type for the expression itself.
2012-03-19 01:36:13 +01:00
// FIXME: I should at this point try harder to find an
// operator that has the proper argument list and use this
// here, but for now we leave it for the back-end to figure out.
#if 0
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
cerr << get_fileline() << ": internal error: I don't know how to resolve types of generic binary expressions." << endl;
Properly elaborate argument types for binary relation expressions. The argument types of binary relation expressions are decoupled from the return type for the expression itself.
2012-03-19 01:36:13 +01:00
#endif
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
return 0;
}
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
int ExpBinary::elaborate_exprs(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
errors += operand1_->elaborate_expr(ent, arc, ltype);
errors += operand2_->elaborate_expr(ent, arc, ltype);
return errors;
}
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
/*
* the default fit_type method for unary operator expressions is to
* return the fit_type for the operand. The assumption is that the
* operator doesn't change the type.
*/
const VType*ExpUnary::fit_type(Entity*ent, Architecture*arc, const VTypeArray*atype) const
{
return operand1_->fit_type(ent, arc, atype);
}
const VType*ExpAggregate::probe_type(Entity*ent, Architecture*arc) const
{
return Expression::probe_type(ent, arc);
}
const VType*ExpAggregate::fit_type(Entity*, Architecture*, const VTypeArray*host) const
{
ivl_assert(*this, elements_.size() == 1);
size_t choice_count = elements_[0]->count_choices();
ivl_assert(*this, choice_count > 0);
vector<choice_element> ce (choice_count);
elements_[0]->map_choices(&ce[0]);
ivl_assert(*this, ce.size() == 1);
prange_t*prange = ce[0].choice->range_expressions();
ivl_assert(*this, prange);
Expression*use_msb = prange->msb();
Expression*use_lsb = prange->lsb();
ivl_assert(*this, host->dimensions() == 1);
vector<VTypeArray::range_t> range (1);
range[0] = VTypeArray::range_t(use_msb, use_lsb);
const VTypeArray*res = new VTypeArray(host->element_type(), range);
return res;
}
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
int ExpAggregate::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
if (ltype == 0) {
Spelling fixes to vhdlpp tree Mostly comments as usual, but one error message is changed.
2012-05-14 18:58:49 +02:00
cerr << get_fileline() << ": error: Elaboration of aggregate types needs well known type context?" << endl;
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
return 1;
}
set_type(ltype);
VHDL named types work in more places.
2012-05-06 01:55:29 +02:00
while (const VTypeDef*cur = dynamic_cast<const VTypeDef*>(ltype)) {
ltype = cur->peek_definition();
}
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
if (const VTypeArray*larray = dynamic_cast<const VTypeArray*>(ltype)) {
return elaborate_expr_array_(ent, arc, larray);
}
cerr << get_fileline() << ": internal error: I don't know how to elaborate aggregate expressions. type=" << typeid(*ltype).name() << endl;
return 1;
}
/*
* Elaboration of array aggregates is elaboration of the element
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
* expressions (the elements_ member) using the element type as the
* ltype for the subexpression.
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
*/
int ExpAggregate::elaborate_expr_array_(Entity*ent, Architecture*arc, const VTypeArray*ltype)
{
const VType*element_type = ltype->element_type();
int errors = 0;
size_t choice_count = 0;
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
// Figure out how many total elements we have here. Note that
// each parsed element may be bound to multiple choices, so
// account for that.
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
for (size_t edx = 0 ; edx < elements_.size() ; edx += 1) {
element_t*ecur = elements_[edx];
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
if (ecur->count_choices() == 0)
choice_count += 1;
else
choice_count += ecur->count_choices();
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
}
aggregate_.resize(choice_count);
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
// Translate the elements_ array to the aggregate_ array. In
// the target array, each expression is attached to a single
// choice.
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
size_t cdx = 0;
for (size_t edx = 0 ; edx < elements_.size() ; edx += 1) {
element_t*ecur = elements_[edx];
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
if (ecur->count_choices() == 0) {
// positional associations have no "choice"
// associated with them.
aggregate_[cdx].choice = 0;
aggregate_[cdx].expr = ecur->extract_expression();
aggregate_[cdx].alias_flag;
cdx += 1;
} else {
ecur->map_choices(&aggregate_[cdx]);
cdx += ecur->count_choices();
}
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
}
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, cdx == choice_count);
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
// Now run through the more convenient mapping and elaborate
// all the expressions that I find.
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
for (size_t idx = 0 ; idx < aggregate_.size() ; idx += 1) {
if (aggregate_[idx].alias_flag)
continue;
errors += aggregate_[idx].expr->elaborate_expr(ent, arc, element_type);
}
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
// done with the obsolete elements_ vector.
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
elements_.clear();
Handle VHDL records. Elaborate records and emit them as packed SV records. Also handle record members so handle name prefixes. While we are at it, handle some cases of array aggregate expressions.
2012-04-09 04:06:58 +02:00
Handle the basics of aggregate expressions This takes care of the parser support, and a shell of the elaboration. Handle some special cases all the way through.
2011-09-04 02:11:55 +02:00
return errors;
}
void ExpAggregate::element_t::map_choices(ExpAggregate::choice_element*dst)
{
for (size_t idx = 0 ; idx < fields_.size() ; idx += 1) {
dst->choice = fields_[idx];
dst->expr = val_;
dst->alias_flag = (idx != 0);
dst += 1;
}
}
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
int ExpArithmetic::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
if (ltype == 0) {
ltype = probe_type(ent, arc);
}
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, ltype != 0);
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
errors += elaborate_exprs(ent, arc, ltype);
return errors;
}
Evaluate VHDL <name>'length attribute at compile time.
2011-09-19 02:45:06 +02:00
const VType* ExpAttribute::probe_type(Entity*ent, Architecture*arc) const
{
base_->probe_type(ent, arc);
if (name_ == "length") {
return primitive_INTEGER;
}
return 0;
}
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
int ExpAttribute::elaborate_expr(Entity*ent, Architecture*arc, const VType*)
{
int errors = 0;
const VType*sub_type = base_->probe_type(ent, arc);
errors += base_->elaborate_expr(ent, arc, sub_type);
return errors;
}
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
const VType*ExpBitstring::fit_type(Entity*, Architecture*, const VTypeArray*atype) const
{
// Really should check that this string can work with the
// array element type?
return atype->element_type();
}
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
int ExpBitstring::elaborate_expr(Entity*, Architecture*, const VType*)
{
int errors = 0;
return errors;
}
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
const VType*ExpCharacter::fit_type(Entity*, Architecture*, const VTypeArray*atype) const
{
// Really should check that this character can work with the
// array element type?
return atype->element_type();
}
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
int ExpCharacter::elaborate_expr(Entity*, Architecture*, const VType*ltype)
{
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, ltype != 0);
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
set_type(ltype);
return 0;
}
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
/*
* I don't know how to probe the type of a concatenation, quite yet.
*/
const VType*ExpConcat::probe_type(Entity*, Architecture*) const
{
ivl_assert(*this, 0);
return 0;
}
int ExpConcat::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
if (ltype == 0) {
ltype = probe_type(ent, arc);
}
ivl_assert(*this, ltype != 0);
if (const VTypeArray*atype = dynamic_cast<const VTypeArray*>(ltype)) {
errors += elaborate_expr_array_(ent, arc, atype);
} else {
errors += operand1_->elaborate_expr(ent, arc, ltype);
errors += operand2_->elaborate_expr(ent, arc, ltype);
}
return errors;
}
int ExpConcat::elaborate_expr_array_(Entity*ent, Architecture*arc, const VTypeArray*atype)
{
int errors = 0;
// For now, only support single-dimension arrays here.
ivl_assert(*this, atype->dimensions() == 1);
const VType*type1 = operand1_->fit_type(ent, arc, atype);
ivl_assert(*this, type1);
const VType*type2 = operand2_->fit_type(ent, arc, atype);
ivl_assert(*this, type2);
errors += operand1_->elaborate_expr(ent, arc, type1);
errors += operand2_->elaborate_expr(ent, arc, type2);
return errors;
}
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
const VType* ExpConditional::probe_type(Entity*, Architecture*) const
{
return 0;
}
int ExpConditional::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
if (ltype == 0)
ltype = probe_type(ent, arc);
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, ltype);
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
set_type(ltype);
/* Note that the type for the condition expression need not
have anything to do with the type of this expression. */
errors += cond_->elaborate_expr(ent, arc, 0);
for (list<Expression*>::const_iterator cur = true_clause_.begin()
; cur != true_clause_.end() ; ++cur) {
errors += (*cur)->elaborate_expr(ent, arc, ltype);
}
Add support for nested when/else expressions.
2012-03-24 18:23:50 +01:00
for (list<else_t*>::const_iterator cur = else_clause_.begin()
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
; cur != else_clause_.end() ; ++cur) {
Add support for nested when/else expressions.
2012-03-24 18:23:50 +01:00
errors += (*cur)->elaborate_expr(ent, arc, ltype);
}
return errors;
}
int ExpConditional::else_t::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
if (cond_)
errors += cond_->elaborate_expr(ent, arc, 0);
for (list<Expression*>::const_iterator cur = true_clause_.begin()
; cur != true_clause_.end() ; ++cur) {
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
errors += (*cur)->elaborate_expr(ent, arc, ltype);
}
return errors;
}
Basic vhdl elaboration for unary not operator.
2011-09-19 00:13:30 +02:00
int ExpFunc::elaborate_expr(Entity*ent, Architecture*arc, const VType*)
Handle a few built-in functions internally. The "unsigned" and "std_logic_vector" functions are internal functions and VHDL and can be handled internally in the code generator.
2011-08-29 00:30:45 +02:00
{
int errors = 0;
for (size_t idx = 0 ; idx < argv_.size() ; idx += 1) {
const VType*tmp = argv_[idx]->probe_type(ent, arc);
errors += argv_[idx]->elaborate_expr(ent, arc, tmp);
}
return errors;
}
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
const VType* ExpInteger::probe_type(Entity*, Architecture*) const
{
return primitive_INTEGER;
}
Elaborate and emit vhdl elsif sections. The IfStatement contains a list of elsif sections that need to be elaborated/emitted in the middle of the true and false clauses.
2011-06-23 03:13:40 +02:00
int ExpInteger::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
if (ltype == 0) {
ltype = probe_type(ent, arc);
}
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, ltype != 0);
Elaborate and emit vhdl elsif sections. The IfStatement contains a list of elsif sections that need to be elaborated/emitted in the middle of the true and false clauses.
2011-06-23 03:13:40 +02:00
return errors;
}
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
int ExpLogical::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
if (ltype == 0) {
ltype = probe_type(ent, arc);
}
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, ltype != 0);
Conditional statements and expressions Elaborate and emit a variety of conditional constructs. Fix up type handling for some expression types Elaborate continuous signal assignments.
2011-06-12 19:51:31 +02:00
errors += elaborate_exprs(ent, arc, ltype);
return errors;
}
Probe type of ExpName with a record prefix.
2012-04-02 03:48:19 +02:00
const VType* ExpName::probe_prefix_type_(Entity*ent, Architecture*arc) const
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
{
Parse name prefix syntax for record member reference. When signals/variables are records, they are often referenced by their members, using a prefix.name syntax. Parse that syntax and generate "sorry" messages in elaboration.
2012-04-01 01:29:40 +02:00
if (prefix_.get()) {
Probe type of ExpName with a record prefix.
2012-04-02 03:48:19 +02:00
cerr << get_fileline() << ": sorry: I do not know how to support nested prefix parts." << endl;
return 0;
}
const VType*type = probe_type(ent, arc);
return type;
}
/*
* This method is the probe_type() imlementation for ExpName objects
* that have prefix parts. In this case we try to get the type of the
* prefix and interpret the name in that context.
*/
const VType* ExpName::probe_prefixed_type_(Entity*ent, Architecture*arc) const
{
// First, get the type of the prefix.
const VType*prefix_type = prefix_->probe_prefix_type_(ent, arc);
if (prefix_type == 0) {
Parse name prefix syntax for record member reference. When signals/variables are records, they are often referenced by their members, using a prefix.name syntax. Parse that syntax and generate "sorry" messages in elaboration.
2012-04-01 01:29:40 +02:00
return 0;
}
Probe type of ExpName with a record prefix.
2012-04-02 03:48:19 +02:00
// If the prefix type is a record, then the current name is
// the name of a member.
if (const VTypeRecord*pref_record = dynamic_cast<const VTypeRecord*> (prefix_type)) {
const VTypeRecord::element_t*element = pref_record->element_by_name(name_);
ivl_assert(*this, element);
const VType*element_type = element->peek_type();
ivl_assert(*this, element_type);
return element_type;
}
cerr << get_fileline() << ": sorry: I don't know how to probe "
<< "prefix type " << typeid(*prefix_type).name()
<< " of " << name_ << "." << endl;
return 0;
}
const VType* ExpName::probe_type(Entity*ent, Architecture*arc) const
{
if (prefix_.get())
return probe_prefixed_type_(ent, arc);
Put off array bound evaluation / describe entity generics as parameters Entity generics are easily implemented as module parameters, so make it so. Give the parameters their default values from the generic declaration. Array bounds may use values that cannot be evaluated right away, so put off their evaluation.
2011-10-16 02:41:48 +02:00
if (const InterfacePort*cur = ent->find_port(name_)) {
ivl_assert(*this, cur->type);
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
return cur->type;
Put off array bound evaluation / describe entity generics as parameters Entity generics are easily implemented as module parameters, so make it so. Give the parameters their default values from the generic declaration. Array bounds may use values that cannot be evaluated right away, so put off their evaluation.
2011-10-16 02:41:48 +02:00
}
if (const InterfacePort*cur = ent->find_generic(name_)) {
ivl_assert(*this, cur->type);
return cur->type;
}
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
if (Signal*sig = arc->find_signal(name_))
return sig->peek_type();
Parse function calls, and detect type case expressions. Type cast expressions and some function calls are syntactically identical to array element select, so we can only tell the difference by looking up the name of the identifier being selected. If it is a type name, then create an ExpCast instead of an ExpName object. Also, parse and emit vector part selects.
2011-08-22 01:52:18 +02:00
if (Variable*var = arc->find_variable(name_))
return var->peek_type();
Better handle type probe of relation arguments.
2011-06-12 20:35:04 +02:00
const VType*ctype = 0;
Expression*cval = 0;
if (arc->find_constant(name_, ctype, cval))
return ctype;
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
cerr << get_fileline() << ": error: Signal/variable " << name_
<< " not found in this context." << endl;
return 0;
}
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
const VType* ExpName::fit_type(Entity*ent, Architecture*arc, const VTypeArray*)const
{
return probe_type(ent, arc);
}
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
int ExpName::elaborate_expr(Entity*, Architecture*, const VType*ltype)
{
Properly elaborate argument types for binary relation expressions. The argument types of binary relation expressions are decoupled from the return type for the expression itself.
2012-03-19 01:36:13 +01:00
if (ltype) {
ivl_assert(*this, ltype != 0);
set_type(ltype);
}
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
return 0;
}
const VType* ExpNameALL::probe_type(Entity*, Architecture*) const
{
return 0;
}
const VType* ExpRelation::probe_type(Entity*ent, Architecture*arc) const
{
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
/* const VType*type1 = */ peek_operand1()->probe_type(ent, arc);
/* const VType*type2 = */ peek_operand2()->probe_type(ent, arc);
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
Proper expression type for vhdl relation expressions.
2011-10-16 20:02:07 +02:00
return primitive_BOOLEAN;
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
}
int ExpRelation::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype)
{
int errors = 0;
if (ltype == 0) {
ltype = probe_type(ent, arc);
}
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, ltype != 0);
Properly elaborate argument types for binary relation expressions. The argument types of binary relation expressions are decoupled from the return type for the expression itself.
2012-03-19 01:36:13 +01:00
// The type of the operands must match, but need not match the
// type for the ExpRelation itself. So get the operand type
// separately.
const VType*otype = ExpBinary::probe_type(ent, arc);
errors += elaborate_exprs(ent, arc, otype);
Elaboration of r-value expressions R-value expressions are more general then L-value expressions, in that the expression type may be a bit more complex. If the R-value expression is part of an assignment, then elaborate with the constrained type from the L-value. In other cases, where the expression type is not as obvious, use expression type probes to figure out the type of the expression and elaborate using that calculated type.
2011-05-31 04:17:40 +02:00
return errors;
}
Add String Expression to the VHDL parser
2011-07-05 12:03:30 +02:00
Reword concat to handle aggregate arguments. When concatenation expressions have aggregate arguments, we need to get the type of the result down to the aggregate expressions so that it can know how to interpret the elements.
2012-04-22 20:42:16 +02:00
/*
* When a string appears in a concatenation, then the type of the
* string is an array with the same element type of the concatenation,
* but with elements for each character of the string.
*/
const VType*ExpString::fit_type(Entity*, Architecture*, const VTypeArray*atype) const
{
vector<VTypeArray::range_t> range (atype->dimensions());
// Generate an array range for this string
ivl_assert(*this, range.size() == 1);
ExpInteger*use_msb = new ExpInteger(value_.size());
ExpInteger*use_lsb = new ExpInteger(0);
FILE_NAME(use_msb, this);
FILE_NAME(use_lsb, this);
range[0] = VTypeArray::range_t(use_msb, use_lsb);
VTypeArray*type = new VTypeArray(atype->element_type(), range);
return type;
}
Add String Expression to the VHDL parser
2011-07-05 12:03:30 +02:00
int ExpString::elaborate_expr(Entity*, Architecture*, const VType*ltype)
{
Distinguish bit selects of entity ports from function calls. Besides variables and signals, a name with a bit select may be an entity port. Distinguish these from function calls.
2011-09-12 00:28:58 +02:00
ivl_assert(*this, ltype != 0);
Add String Expression to the VHDL parser
2011-07-05 12:03:30 +02:00
set_type(ltype);
return 0;
}
Basic vhdl elaboration for unary not operator.
2011-09-19 00:13:30 +02:00
int ExpUNot::elaborate_expr(Entity*, Architecture*, const VType*ltype)
{
ivl_assert(*this, ltype != 0);
set_type(ltype);
return 0;
}