Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
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Chris Baker a5427d704a icebox_vlog: use proper Verilog-2001 module declarations
Resolves #328
Summary:
- By default emit Verilog-2001 style module declarations with direction
  and signal type defined in the module prototype and not in the body of
  the module
- Add -C option to output Verilog-1995 module declarations for
  compatibility with older toolchains
- Add some comments to the file to assist future maintainers

Background:
Currently, icebox_vlog outputs a mixed-style module declaration in which
it puts the port direction in the module prototype and later declares
the signals as ports or wires.
```verilog
module chip (input pin1, output pin2);

wire pin1;
reg pin2 = 0;
```

The inclusion of the direction in the module prototype is a feature of
newer Verilog-2001 specification.

It seems probable that older versions of Icarus Verilog had some leeway
in handling this mixed-style of declaration. But, it seems that at least
the version included in newer Ubuntu distributions considers this to be
a syntax error.

In this commit, the module declaration above will be emitted as:
```verilog
module chip (input wire pin1, output reg pin2 = 0);
```

Or if you sepcificy the -C option for Verilog-1995 compatibility:
```verilog
module chip (pin1, pin2);
input pin1;
output pin2;

wire pin1;
reg pin2 = 0;
```
2024-04-21 14:33:23 -04:00
docs Update BRAM NegClk info based on latest testing 2023-03-20 09:12:23 +01:00
examples Replaced instances of `arachne-pnr` with the `nextpnr-ice40` equivalent 2022-09-15 06:32:45 -04:00
icebox icebox_vlog: use proper Verilog-2001 module declarations 2024-04-21 14:33:23 -04:00
icebram icebram: don't use exceptions. 2023-02-18 11:33:40 +00:00
icecompr Squelch trailing whitespace 2017-08-01 14:43:15 +02:00
icefuzz Update variable name to PYTHON3 2021-09-06 11:11:52 +02:00
icemulti Add more build products to .gitignore. 2021-03-05 12:43:57 +00:00
icepack Add more build products to .gitignore. 2021-03-05 12:43:57 +00:00
icepll Change help message 2022-05-30 10:14:13 +02:00
iceprog Merge pull request #283 from smunaut/misc 2022-05-30 10:09:53 +02:00
icetime Merge pull request #291 from maikmerten/master 2022-05-30 10:08:40 +02:00
.gitignore Added/improved support for mxe-based win32 cross builds 2016-02-14 13:47:27 +01:00
COPYING Update COPYING 2022-06-03 10:31:05 +02:00
CodeOfConduct Added CodeOfConduct 2016-02-01 18:54:09 +01:00
Makefile Make iceprog optional. 2019-08-31 14:03:14 +00:00
README Update URL for web site. 2021-11-28 19:26:21 +00:00
config.mk Update variable name to PYTHON3 2021-09-06 11:11:52 +02:00

README

Project IceStorm aims at documenting the bitstream format of Lattice iCE40
FPGAs and providing simple tools for analyzing and creating bitstream files.

See http://bygone.clairexen.net/icestorm/ for more information.

Most of Project IceStorm is licensed under the ISC license:

#  Permission to use, copy, modify, and/or distribute this software for any
#  purpose with or without fee is hereby granted, provided that the above
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