mirror of https://github.com/YosysHQ/icestorm.git
a5427d704a
Resolves #328 Summary: - By default emit Verilog-2001 style module declarations with direction and signal type defined in the module prototype and not in the body of the module - Add -C option to output Verilog-1995 module declarations for compatibility with older toolchains - Add some comments to the file to assist future maintainers Background: Currently, icebox_vlog outputs a mixed-style module declaration in which it puts the port direction in the module prototype and later declares the signals as ports or wires. ```verilog module chip (input pin1, output pin2); wire pin1; reg pin2 = 0; ``` The inclusion of the direction in the module prototype is a feature of newer Verilog-2001 specification. It seems probable that older versions of Icarus Verilog had some leeway in handling this mixed-style of declaration. But, it seems that at least the version included in newer Ubuntu distributions considers this to be a syntax error. In this commit, the module declaration above will be emitted as: ```verilog module chip (input wire pin1, output reg pin2 = 0); ``` Or if you sepcificy the -C option for Verilog-1995 compatibility: ```verilog module chip (pin1, pin2); input pin1; output pin2; wire pin1; reg pin2 = 0; ``` |
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| .. | ||
| .gitignore | ||
| Makefile | ||
| icebox.py | ||
| icebox_asc2hlc.py | ||
| icebox_chipdb.py | ||
| icebox_colbuf.py | ||
| icebox_diff.py | ||
| icebox_explain.py | ||
| icebox_hlc2asc.py | ||
| icebox_hlcsort.py | ||
| icebox_html.py | ||
| icebox_maps.py | ||
| icebox_stat.py | ||
| icebox_vlog.py | ||
| iceboxdb.py | ||
| tc_logic_xpr.py | ||
| tc_rxlat_netnames.py | ||
| tc_xlat_netnames.py | ||