Simon Schubert be0bca0230 u4k: add SMCCLK cell location ...

icecube uses SMCCLK.CLK to "legalize" output cells.  Unclear what this
is for, but it appears in almost all outputs.

2019-02-22 22:35:55 +01:00

..

pinloc

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

tests

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

.gitignore

Updated 5k timing data, icetime regression fix

2018-01-29 14:02:37 +00:00

cached_dsp0_5k.txt

Create icefuzz scripts for DSP and 5k

2017-11-17 15:07:52 +00:00

cached_dsp1_5k.txt

Create icefuzz scripts for DSP and 5k

2017-11-17 15:07:52 +00:00

cached_dsp2_5k.txt

Create icefuzz scripts for DSP and 5k

2017-11-17 15:07:52 +00:00

cached_dsp3_5k.txt

Add missing 5k BRAM bits

2017-11-17 18:29:14 +00:00

cached_io.txt

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

cached_ipcon_5k.txt

Create icefuzz scripts for DSP and 5k

2017-11-17 15:07:52 +00:00

cached_logic.txt

Imported full dev sources

2015-07-18 13:10:40 +02:00

cached_ramb_8k.txt

Added 8k timing data

2015-10-06 09:12:26 +02:00

cached_ramb.txt

Imported full dev sources

2015-07-18 13:10:40 +02:00

cached_ramt_8k.txt

icefuzz improvements, refuzz timings

2016-01-16 16:17:56 +01:00

cached_ramt.txt

icefuzz improvements, refuzz timings

2016-01-16 16:17:56 +01:00

check.sh

Renamed IceBox .txt files to .asc files

2016-01-01 15:08:41 +01:00

database.py

Remove seperate 5k RAM DB and share with 8k instead

2018-01-16 15:17:20 +00:00

export.py

Remove seperate 5k RAM DB and share with 8k instead

2018-01-16 15:17:20 +00:00

extract.py

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

fuzzconfig.py

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

glbcheck.py

Create icefuzz scripts for DSP and 5k

2017-11-17 15:07:52 +00:00

glbmapbits.py

icefuzz: python 3

2015-08-22 09:42:57 +02:00

icecube.sh

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

make_aig.py

Fix some bugs in two of the icefuzz make_*.py scripts

2017-07-31 15:56:58 +02:00

make_binop.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_cluster.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_dsp.py

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

make_fanout.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_fflogic.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_gbio2.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_gbio.py

Fix some bugs in two of the icefuzz make_*.py scripts

2017-07-31 15:56:58 +02:00

make_io.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_iopack.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_logic.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_mem.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_mesh.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_pin2pin.py

Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok.

2017-07-02 15:38:44 -07:00

make_pll.py

Squelch trailing whitespace

2017-08-01 14:43:15 +02:00

make_prim.py

Fix case where make_prim allocates all global buffer pins

2017-10-20 15:18:39 +01:00

make_ram40.py

Fix make_ram40 for UltraPlus

2017-10-20 16:27:06 +01:00

make_uip.py

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

make_upip.py

Create icefuzz scripts for DSP and 5k

2017-11-17 15:07:52 +00:00

Makefile

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

rename_dsps.py

Seperate different DSP configs in timing data

2018-01-22 16:34:51 +00:00

runloop.sh

Fixed icefuzz/runloop.sh for git

2016-01-01 16:28:57 +01:00

timings_hx1k.txt

Timing models for LP and HX devices

2016-02-01 23:32:03 +01:00

timings_hx8k.txt

Timing models for LP and HX devices

2016-02-01 23:32:03 +01:00

timings_loop.sh

Updated 5k timing data, icetime regression fix

2018-01-29 14:02:37 +00:00

timings_lp1k.txt

Timing models for LP and HX devices

2016-02-01 23:32:03 +01:00

timings_lp8k.txt

Timing models for LP and HX devices

2016-02-01 23:32:03 +01:00

timings_lp384.txt

icefuzz data and test scripts for LP384-CM49

2017-03-10 02:09:46 +01:00

timings_u4k.txt

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

timings_up5k.txt

Updated 5k timing data, icetime regression fix

2018-01-29 14:02:37 +00:00

timings.py

Seperate different DSP configs in timing data

2018-01-22 16:34:51 +00:00

tmedges.txt

u4k: add SMCCLK cell location

2019-02-22 22:35:55 +01:00

tmedges.ys

u4k: add SMCCLK cell location

2019-02-22 22:35:55 +01:00