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Timing models for LP and HX devices

This commit is contained in:
Clifford Wolf 2016-02-01 23:32:03 +01:00
parent 8b6116523b
commit 81c33a343f
18 changed files with 1255 additions and 650 deletions
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6
examples/hx8kboard/Makefile
View File

@ -1,6 +1,6 @@
PROJ = example
PIN_DEF = hx8kboard.pcf
DEVICE = 8k
DEVICE = hx8k
all: $(PROJ).rpt $(PROJ).bin
@ -8,13 +8,13 @@ all: $(PROJ).rpt $(PROJ).bin
yosys -p 'synth_ice40 -top top -blif $@' $<
%.asc: $(PIN_DEF) %.blif
arachne-pnr -d $(DEVICE) -o $@ -p $^
arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^
%.bin: %.asc
icepack $< $@
%.rpt: %.asc
icetime -mtr $@ $<
icetime -d $(DEVICE) -mtr $@ $<
prog: $(PROJ).bin
iceprog $<

4
examples/iceblink/.gitignore vendored Normal file
View File

@ -0,0 +1,4 @@
example.bin
example.blif
example.asc
example.rpt

9
examples/iceblink/Makefile
View File

@ -1,18 +1,21 @@
PROJ = example
PIN_DEF = iceblink.pcf
DEVICE = 1k
DEVICE = hx1k
all: $(PROJ).bin
all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v
yosys -p 'synth_ice40 -top top -blif $@' $<
%.asc: $(PIN_DEF) %.blif
arachne-pnr -d $(DEVICE) -o $@ -p $^ -P vq100
arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P vq100
%.bin: %.asc
icepack $< $@
%.rpt: %.asc
icetime -d $(DEVICE) -mtr $@ $<
prog: $(PROJ).bin
iCEburn.py -e -v -w $<

6
examples/icestick/Makefile
View File

@ -1,6 +1,6 @@
PROJ = example
PIN_DEF = icestick.pcf
DEVICE = 1k
DEVICE = hx1k
all: $(PROJ).rpt $(PROJ).bin
@ -8,13 +8,13 @@ all: $(PROJ).rpt $(PROJ).bin
yosys -p 'synth_ice40 -top top -blif $@' $<
%.asc: $(PIN_DEF) %.blif
arachne-pnr -d $(DEVICE) -o $@ -p $^
arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^
%.bin: %.asc
icepack $< $@
%.rpt: %.asc
icetime -mtr $@ $<
icetime -d $(DEVICE) -mtr $@ $<
prog: $(PROJ).bin
iceprog $<

5
icefuzz/.gitignore vendored
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@ -2,9 +2,12 @@
*.glb
*.psb
*.tmp/
*.txt
*.asc
*.vsb
*.sdf
/work_*/
__pycache__
bitdata_*.txt
data_*.txt
database_*.txt
timings_*.html

28
icefuzz/Makefile
View File

@ -1,5 +1,6 @@
include ../config.mk
export LC_ALL=C
export ICE_SBTIMER_LP=1
TESTS =
TESTS += binop
@ -40,22 +41,28 @@ endif
timings:
ifeq ($(EIGTHK),_8k)
cp tmedges_8k.txt tmedges.tmp
cp tmedges.txt tmedges.tmp
set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
sort -u tmedges.tmp > tmedges_8k.txt && rm -f tmedges.tmp
python3 timings.py -t timings_8k.txt work_*/*.sdf > timings_8k.new
mv timings_8k.new timings_8k.txt
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
python3 timings.py -t timings_hx8k.txt work_*/*.sdf > timings_hx8k.new
mv timings_hx8k.new timings_hx8k.txt
python3 timings.py -t timings_lp8k.txt work_*/*.slp > timings_lp8k.new
mv timings_lp8k.new timings_lp8k.txt
else
cp tmedges_1k.txt tmedges.tmp
cp tmedges.txt tmedges.tmp
set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
sort -u tmedges.tmp > tmedges_1k.txt && rm -f tmedges.tmp
python3 timings.py -t timings_1k.txt work_*/*.sdf > timings_1k.new
mv timings_1k.new timings_1k.txt
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
python3 timings.py -t timings_hx1k.txt work_*/*.sdf > timings_hx1k.new
mv timings_hx1k.new timings_hx1k.txt
python3 timings.py -t timings_lp1k.txt work_*/*.slp > timings_lp1k.new
mv timings_lp1k.new timings_lp1k.txt
endif
timings_html:
python3 timings.py -h tmedges_1k.txt -t timings_1k.txt -l "HX1K with default temp/volt settings" > timings_1k.html
python3 timings.py -h tmedges_8k.txt -t timings_8k.txt -l "HX8K with default temp/volt settings" > timings_8k.html
python3 timings.py -h tmedges.txt -t timings_hx1k.txt -l "HX1K with default temp/volt settings" > timings_hx1k.html
python3 timings.py -h tmedges.txt -t timings_hx8k.txt -l "HX8K with default temp/volt settings" > timings_hx8k.html
python3 timings.py -h tmedges.txt -t timings_lp1k.txt -l "LP1K with default temp/volt settings" > timings_lp1k.html
python3 timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html
data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt
gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new
@ -113,6 +120,7 @@ clean:
rm -rf data_*.txt
rm -rf bitdata_*.txt
rm -rf database_*.txt
rm -rf timings_*.html
.PHONY: database datafiles check clean

8
icefuzz/icecube.sh
View File

@ -263,6 +263,10 @@ fi
# run netlister
"$icecubedir"/sbt_backend/bin/linux/opt/netlister --verilog "$PWD"/outputs/netlist/top_sbt.v --vhdl "$PWD"/outputs/netlist/top_sbt.vhd --lib "$PWD"/netlist/oadb-top --view rt --device "$icecubedir"/sbt_backend/devices/$devfile --splitio --in-sdc-file "$PWD"/outputs/packer/top_pk.sdc --out-sdc-file "$PWD"/outputs/netlist/top_sbt.sdc
if [ -n "$ICE_SBTIMER_LP" ]; then
"$icecubedir"/sbt_backend/bin/linux/opt/sbtimer --des-lib "$PWD"/netlist/oadb-top --lib-file "$icecubedir"/sbt_backend/devices/$libfile --sdc-file "$PWD"/outputs/netlist/top_sbt.sdc --sdf-file "$PWD"/outputs/netlist/top_sbt_lp.sdf --report-file "$PWD"/outputs/netlist/top_timing_lp.rpt --device-file "$icecubedir"/sbt_backend/devices/$devfile --timing-summary
fi
# hacks for sbtimer so it knows what device we are dealing with
ln -fs . sbt
ln -fs . foobar_Implmnt
@ -304,6 +308,10 @@ cp "$1.tmp"/outputs/placer/top_sbt.pcf "$1.psb"
cp "$1.tmp"/outputs/netlist/top_sbt.v "$1.vsb"
cp "$1.tmp"/outputs/netlist/top_sbt.sdf "$1.sdf"
cp "$1.tmp"/outputs/netlist/top_timing.rpt "$1.rpt"
if [ -n "$ICE_SBTIMER_LP" ]; then
cp "$1.tmp"/outputs/netlist/top_sbt_lp.sdf "$1.slp"
cp "$1.tmp"/outputs/netlist/top_timing_lp.rpt "$1.rlp"
fi
$scriptdir/../icepack/iceunpack "$1.bin" "$1.asc"

1
icefuzz/pinloc/.gitignore vendored
View File

@ -4,4 +4,5 @@ pinloc-*.exp.new
pinloc-*.log
pinloc-*.pcf
pinloc-*.rpt
pinloc-*.txt
pinloc-*.v

2
icefuzz/timings.py
View File

@ -3,7 +3,7 @@
import getopt, sys, re
ignore_cells = set([
"ADTTRIBUF", "CascadeBuf", "DL", "GIOBUG", "LUT_MUX", "MUX4",
"ADTTRIBUF", "DL", "GIOBUG", "LUT_MUX", "MUX4",
"PLL40_2_FEEDBACK_PATH_DELAY", "PLL40_2_FEEDBACK_PATH_EXTERNAL",
"PLL40_2_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_2_FEEDBACK_PATH_SIMPLE",
"PLL40_2F_FEEDBACK_PATH_DELAY", "PLL40_2F_FEEDBACK_PATH_EXTERNAL",

3
icefuzz/timings_1k.txt → icefuzz/timings_hx1k.txt
View File

@ -1,3 +1,6 @@
CELL CascadeBuf
IOPATH I O 118.382:130.906:147.283 146.568:162.074:182.35
CELL CascadeMux
IOPATH I O 0:0:0 0:0:0

2
icefuzz/timings_8k.txt → icefuzz/timings_hx8k.txt
View File

@ -1,5 +1,5 @@
CELL CascadeBuf
IOPATH I O 137.402:178.5:217.075 170.116:221:268.76
IOPATH I O 118.382:130.906:147.283 146.568:162.074:182.35
CELL CascadeMux
IOPATH I O 0:0:0 0:0:0

531
icefuzz/timings_lp1k.txt Normal file
View File

@ -0,0 +1,531 @@
CELL CascadeBuf
IOPATH I O 137.402:178.5:217.075 170.116:221:268.76
CELL CascadeMux
IOPATH I O 0:0:0 0:0:0
CELL CEMux
IOPATH I O 562.692:731:888.975 516.892:671.5:816.617
CELL ClkMux
IOPATH I O 287.889:374:454.825 215.917:280.5:341.118
CELL gio2CtrlBuf
IOPATH I O 0:0:0 0:0:0
CELL Glb2LocalMux
IOPATH I O 418.748:544:661.563 333.689:433.5:527.183
CELL GlobalMux
IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706
CELL ICE_CARRY_IN_MUX
IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423
CELL ICE_GB
IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954
CELL InMux
IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
CELL INV
IOPATH I O 0:0:0 0:0:0
CELL IO_PAD
IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990
IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942
IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540
CELL IoInMux
IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
CELL IoSpan4Mux
IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
CELL LocalMux
IOPATH I O 307.518:399.5:485.835 287.889:374:454.825
CELL LogicCell40
HOLD negedge:ce posedge:clk 0:0:0
HOLD negedge:in0 posedge:clk 0:0:0
HOLD negedge:in1 posedge:clk 0:0:0
HOLD negedge:in2 posedge:clk 0:0:0
HOLD negedge:in3 posedge:clk 0:0:0
HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984
HOLD posedge:ce posedge:clk 0:0:0
HOLD posedge:in0 posedge:clk 0:0:0
HOLD posedge:in1 posedge:clk 0:0:0
HOLD posedge:in2 posedge:clk 0:0:0
HOLD posedge:in3 posedge:clk 0:0:0
HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005
RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372
RECOVERY posedge:sr posedge:clk 0:0:0
REMOVAL negedge:sr posedge:clk 0:0:0
REMOVAL posedge:sr posedge:clk 0:0:0
SETUP negedge:ce posedge:clk 0:0:0
SETUP negedge:in0 posedge:clk 372.947:484.5:589.205
SETUP negedge:in1 posedge:clk 353.318:459:558.194
SETUP negedge:in2 posedge:clk 300.975:391:475.498
SETUP negedge:in3 posedge:clk 202.831:263.5:320.445
SETUP negedge:sr posedge:clk 130.859:170:206.738
SETUP posedge:ce posedge:clk 0:0:0
SETUP posedge:in0 posedge:clk 438.376:569.5:692.574
SETUP posedge:in1 posedge:clk 372.947:484.5:589.205
SETUP posedge:in2 posedge:clk 346.775:450.5:547.857
SETUP posedge:in3 posedge:clk 255.174:331.5:403.14
SETUP posedge:sr posedge:clk 189.745:246.5:299.771
IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054
IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531
IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531
IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792
IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194
IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194
IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402
IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846
IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509
IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814
IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14
IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943
IOPATH sr lcout 0:0:0 558.989:726.189:883.125
IOPATH sr lcout 558.963:726.155:883.083 0:0:0
CELL Odrv4
IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
CELL Odrv12
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
CELL PLL40
IOPATH PLLIN PLLOUTCORE *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:*
CELL PLL40_2
IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
CELL PLL40_2F
IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
CELL PRE_IO
HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0
HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0
HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
HOLD negedge:PADIN negedge:INPUTCLK 0:0:0
HOLD negedge:PADIN posedge:INPUTCLK 0:0:0
HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0
HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0
HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
HOLD posedge:PADIN negedge:INPUTCLK 0:0:0
HOLD posedge:PADIN posedge:INPUTCLK 0:0:0
SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369
SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:PADIN negedge:INPUTCLK 1527.97:1985:2413.98
SETUP negedge:PADIN posedge:INPUTCLK 1527.97:1985:2413.98
SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706
SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:PADIN negedge:INPUTCLK 1534.51:1993.5:2424.32
SETUP posedge:PADIN posedge:INPUTCLK 1534.51:1993.5:2424.32
IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48
IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857
IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738
IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108
IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237
IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738
IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738
IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
CELL PRE_IO_GBUF
IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1313.95:1706.97:2075.86 1170.01:1519.97:1848.45
CELL SB_PLL40_2F_CORE
IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:*
CELL SB_PLL40_CORE
IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:*
CELL SB_RAM40_4K
HOLD negedge:MASK[0] posedge:WCLK 0:0:0
HOLD negedge:MASK[1] posedge:WCLK 0:0:0
HOLD negedge:MASK[2] posedge:WCLK 0:0:0
HOLD negedge:MASK[3] posedge:WCLK 0:0:0
HOLD negedge:MASK[4] posedge:WCLK 0:0:0
HOLD negedge:MASK[5] posedge:WCLK 0:0:0
HOLD negedge:MASK[6] posedge:WCLK 0:0:0
HOLD negedge:MASK[7] posedge:WCLK 0:0:0
HOLD negedge:MASK[8] posedge:WCLK 0:0:0
HOLD negedge:MASK[9] posedge:WCLK 0:0:0
HOLD negedge:MASK[10] posedge:WCLK 0:0:0
HOLD negedge:MASK[11] posedge:WCLK 0:0:0
HOLD negedge:MASK[12] posedge:WCLK 0:0:0
HOLD negedge:MASK[13] posedge:WCLK 0:0:0
HOLD negedge:MASK[14] posedge:WCLK 0:0:0
HOLD negedge:MASK[15] posedge:WCLK 0:0:0
HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
HOLD negedge:RE posedge:RCLK 78.5152:102:124.043
HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585
HOLD posedge:MASK[0] posedge:WCLK 0:0:0
HOLD posedge:MASK[1] posedge:WCLK 0:0:0
HOLD posedge:MASK[2] posedge:WCLK 0:0:0
HOLD posedge:MASK[3] posedge:WCLK 0:0:0
HOLD posedge:MASK[4] posedge:WCLK 0:0:0
HOLD posedge:MASK[5] posedge:WCLK 0:0:0
HOLD posedge:MASK[6] posedge:WCLK 0:0:0
HOLD posedge:MASK[7] posedge:WCLK 0:0:0
HOLD posedge:MASK[8] posedge:WCLK 0:0:0
HOLD posedge:MASK[9] posedge:WCLK 0:0:0
HOLD posedge:MASK[10] posedge:WCLK 0:0:0
HOLD posedge:MASK[11] posedge:WCLK 0:0:0
HOLD posedge:MASK[12] posedge:WCLK 0:0:0
HOLD posedge:MASK[13] posedge:WCLK 0:0:0
HOLD posedge:MASK[14] posedge:WCLK 0:0:0
HOLD posedge:MASK[15] posedge:WCLK 0:0:0
HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
HOLD posedge:RE posedge:RCLK 78.5152:102:124.043
HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585
SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803
SETUP negedge:RE posedge:RCLK 91.601:119:144.717
SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781
SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803
SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402
SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803
SETUP posedge:RE posedge:RCLK 91.601:119:144.717
SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781
SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803
SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402
IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1
CELL Sp12to4
IOPATH I O 399.119:518.5:630.552 418.748:544:661.563
CELL Span4Mux_h0
IOPATH I O 137.402:178.5:217.075 130.859:170:206.738
CELL Span4Mux_h1
IOPATH I O 163.573:212.5:258.423 157.03:204:248.086
CELL Span4Mux_h2
IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771
CELL Span4Mux_h3
IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118
CELL Span4Mux_h4
IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161
CELL Span4Mux_v0
IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097
CELL Span4Mux_v1
IOPATH I O 189.745:246.5:299.771 183.202:238:289.434
CELL Span4Mux_v2
IOPATH I O 235.546:306:372.129 235.546:306:372.129
CELL Span4Mux_v3
IOPATH I O 294.432:382.5:465.161 314.061:408:496.172
CELL Span4Mux_v4
IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
CELL Span12Mux_h0
IOPATH I O 130.859:170:206.738 137.402:178.5:217.075
CELL Span12Mux_h1
IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402
CELL Span12Mux_h2
IOPATH I O 150.487:195.5:237.749 157.03:204:248.086
CELL Span12Mux_h3
IOPATH I O 157.03:204:248.086 170.116:221:268.76
CELL Span12Mux_h4
IOPATH I O 183.202:238:289.434 202.831:263.5:320.445
CELL Span12Mux_h5
IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466
CELL Span12Mux_h6
IOPATH I O 235.546:306:372.129 261.717:340:413.477
CELL Span12Mux_h7
IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
CELL Span12Mux_h8
IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531
CELL Span12Mux_h9
IOPATH I O 366.404:476:578.868 405.662:527:640.889
CELL Span12Mux_h10
IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574
CELL Span12Mux_h11
IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269
CELL Span12Mux_h12
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
CELL Span12Mux_v0
IOPATH I O 91.601:119:144.717 98.144:127.5:155.054
CELL Span12Mux_v1
IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054
CELL Span12Mux_v2
IOPATH I O 130.859:170:206.738 143.944:187:227.412
CELL Span12Mux_v3
IOPATH I O 137.402:178.5:217.075 157.03:204:248.086
CELL Span12Mux_v4
IOPATH I O 170.116:221:268.76 196.288:255:310.108
CELL Span12Mux_v5
IOPATH I O 222.46:289:351.455 248.631:323:392.803
CELL Span12Mux_v6
IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814
CELL Span12Mux_v7
IOPATH I O 261.717:340:413.477 294.432:382.5:465.161
CELL Span12Mux_v8
IOPATH I O 333.689:433.5:527.183 366.404:476:578.868
CELL Span12Mux_v9
IOPATH I O 353.318:459:558.194 392.576:510:620.215
CELL Span12Mux_v10
IOPATH I O 366.404:476:578.868 405.662:527:640.889
CELL Span12Mux_v11
IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9
CELL Span12Mux_v12
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
CELL SRMux
IOPATH I O 431.833:561:682.237 333.689:433.5:527.183

531
icefuzz/timings_lp8k.txt Normal file
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@ -0,0 +1,531 @@
CELL CascadeBuf
IOPATH I O 137.402:178.5:217.075 170.116:221:268.76
CELL CascadeMux
IOPATH I O 0:0:0 0:0:0
CELL CEMux
IOPATH I O 562.692:731:888.975 516.892:671.5:816.617
CELL ClkMux
IOPATH I O 287.889:374:454.825 215.917:280.5:341.118
CELL gio2CtrlBuf
IOPATH I O 0:0:0 0:0:0
CELL Glb2LocalMux
IOPATH I O 418.748:544:661.563 333.689:433.5:527.183
CELL GlobalMux
IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706
CELL ICE_CARRY_IN_MUX
IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423
CELL ICE_GB
IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954
CELL InMux
IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
CELL INV
IOPATH I O 0:0:0 0:0:0
CELL IO_PAD
IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990
IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942
IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540
CELL IoInMux
IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
CELL IoSpan4Mux
IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
CELL LocalMux
IOPATH I O 307.518:399.5:485.835 287.889:374:454.825
CELL LogicCell40
HOLD negedge:ce posedge:clk 0:0:0
HOLD negedge:in0 posedge:clk 0:0:0
HOLD negedge:in1 posedge:clk 0:0:0
HOLD negedge:in2 posedge:clk 0:0:0
HOLD negedge:in3 posedge:clk 0:0:0
HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984
HOLD posedge:ce posedge:clk 0:0:0
HOLD posedge:in0 posedge:clk 0:0:0
HOLD posedge:in1 posedge:clk 0:0:0
HOLD posedge:in2 posedge:clk 0:0:0
HOLD posedge:in3 posedge:clk 0:0:0
HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005
RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372
RECOVERY posedge:sr posedge:clk 0:0:0
REMOVAL negedge:sr posedge:clk 0:0:0
REMOVAL posedge:sr posedge:clk 0:0:0
SETUP negedge:ce posedge:clk 0:0:0
SETUP negedge:in0 posedge:clk 372.947:484.5:589.205
SETUP negedge:in1 posedge:clk 353.318:459:558.194
SETUP negedge:in2 posedge:clk 300.975:391:475.498
SETUP negedge:in3 posedge:clk 202.831:263.5:320.445
SETUP negedge:sr posedge:clk 130.859:170:206.738
SETUP posedge:ce posedge:clk 0:0:0
SETUP posedge:in0 posedge:clk 438.376:569.5:692.574
SETUP posedge:in1 posedge:clk 372.947:484.5:589.205
SETUP posedge:in2 posedge:clk 346.775:450.5:547.857
SETUP posedge:in3 posedge:clk 255.174:331.5:403.14
SETUP posedge:sr posedge:clk 189.745:246.5:299.771
IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054
IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531
IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531
IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792
IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194
IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194
IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402
IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846
IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509
IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814
IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14
IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943
IOPATH sr lcout 0:0:0 558.989:726.189:883.125
IOPATH sr lcout 558.963:726.155:883.083 0:0:0
CELL Odrv4
IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
CELL Odrv12
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
CELL PLL40
IOPATH PLLIN PLLOUTCORE *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:*
CELL PLL40_2
IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
CELL PLL40_2F
IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
CELL PRE_IO
HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0
HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0
HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
HOLD negedge:PADIN negedge:INPUTCLK 0:0:0
HOLD negedge:PADIN posedge:INPUTCLK 0:0:0
HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0
HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0
HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
HOLD posedge:PADIN negedge:INPUTCLK 0:0:0
HOLD posedge:PADIN posedge:INPUTCLK 0:0:0
SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369
SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369
SETUP negedge:PADIN negedge:INPUTCLK 1758.87:2284.97:2778.77
SETUP negedge:PADIN posedge:INPUTCLK 1758.87:2284.97:2778.77
SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706
SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
SETUP posedge:PADIN negedge:INPUTCLK 1765.41:2293.47:2789.11
SETUP posedge:PADIN posedge:INPUTCLK 1765.41:2293.47:2789.11
IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48
IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857
IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738
IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108
IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237
IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738
IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738
IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
CELL PRE_IO_GBUF
IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1737.34:2257:2744.76 1593.4:2070:2517.35
CELL SB_PLL40_2F_CORE
IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:*
CELL SB_PLL40_CORE
IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:*
IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:*
CELL SB_RAM40_4K
HOLD negedge:MASK[0] posedge:WCLK 0:0:0
HOLD negedge:MASK[1] posedge:WCLK 0:0:0
HOLD negedge:MASK[2] posedge:WCLK 0:0:0
HOLD negedge:MASK[3] posedge:WCLK 0:0:0
HOLD negedge:MASK[4] posedge:WCLK 0:0:0
HOLD negedge:MASK[5] posedge:WCLK 0:0:0
HOLD negedge:MASK[6] posedge:WCLK 0:0:0
HOLD negedge:MASK[7] posedge:WCLK 0:0:0
HOLD negedge:MASK[8] posedge:WCLK 0:0:0
HOLD negedge:MASK[9] posedge:WCLK 0:0:0
HOLD negedge:MASK[10] posedge:WCLK 0:0:0
HOLD negedge:MASK[11] posedge:WCLK 0:0:0
HOLD negedge:MASK[12] posedge:WCLK 0:0:0
HOLD negedge:MASK[13] posedge:WCLK 0:0:0
HOLD negedge:MASK[14] posedge:WCLK 0:0:0
HOLD negedge:MASK[15] posedge:WCLK 0:0:0
HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
HOLD negedge:RE posedge:RCLK 78.5152:102:124.043
HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585
HOLD posedge:MASK[0] posedge:WCLK 0:0:0
HOLD posedge:MASK[1] posedge:WCLK 0:0:0
HOLD posedge:MASK[2] posedge:WCLK 0:0:0
HOLD posedge:MASK[3] posedge:WCLK 0:0:0
HOLD posedge:MASK[4] posedge:WCLK 0:0:0
HOLD posedge:MASK[5] posedge:WCLK 0:0:0
HOLD posedge:MASK[6] posedge:WCLK 0:0:0
HOLD posedge:MASK[7] posedge:WCLK 0:0:0
HOLD posedge:MASK[8] posedge:WCLK 0:0:0
HOLD posedge:MASK[9] posedge:WCLK 0:0:0
HOLD posedge:MASK[10] posedge:WCLK 0:0:0
HOLD posedge:MASK[11] posedge:WCLK 0:0:0
HOLD posedge:MASK[12] posedge:WCLK 0:0:0
HOLD posedge:MASK[13] posedge:WCLK 0:0:0
HOLD posedge:MASK[14] posedge:WCLK 0:0:0
HOLD posedge:MASK[15] posedge:WCLK 0:0:0
HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
HOLD posedge:RE posedge:RCLK 78.5152:102:124.043
HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585
SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803
SETUP negedge:RE posedge:RCLK 91.601:119:144.717
SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781
SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781
SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803
SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402
SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803
SETUP posedge:RE posedge:RCLK 91.601:119:144.717
SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781
SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781
SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803
SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402
IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1
IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1
CELL Sp12to4
IOPATH I O 399.119:518.5:630.552 418.748:544:661.563
CELL Span4Mux_h0
IOPATH I O 137.402:178.5:217.075 130.859:170:206.738
CELL Span4Mux_h1
IOPATH I O 163.573:212.5:258.423 157.03:204:248.086
CELL Span4Mux_h2
IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771
CELL Span4Mux_h3
IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118
CELL Span4Mux_h4
IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161
CELL Span4Mux_v0
IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097
CELL Span4Mux_v1
IOPATH I O 189.745:246.5:299.771 183.202:238:289.434
CELL Span4Mux_v2
IOPATH I O 235.546:306:372.129 235.546:306:372.129
CELL Span4Mux_v3
IOPATH I O 294.432:382.5:465.161 314.061:408:496.172
CELL Span4Mux_v4
IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
CELL Span12Mux_h0
IOPATH I O 130.859:170:206.738 137.402:178.5:217.075
CELL Span12Mux_h1
IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402
CELL Span12Mux_h2
IOPATH I O 150.487:195.5:237.749 157.03:204:248.086
CELL Span12Mux_h3
IOPATH I O 157.03:204:248.086 170.116:221:268.76
CELL Span12Mux_h4
IOPATH I O 183.202:238:289.434 202.831:263.5:320.445
CELL Span12Mux_h5
IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466
CELL Span12Mux_h6
IOPATH I O 235.546:306:372.129 261.717:340:413.477
CELL Span12Mux_h7
IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
CELL Span12Mux_h8
IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531
CELL Span12Mux_h9
IOPATH I O 366.404:476:578.868 405.662:527:640.889
CELL Span12Mux_h10
IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574
CELL Span12Mux_h11
IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269
CELL Span12Mux_h12
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
CELL Span12Mux_v0
IOPATH I O 91.601:119:144.717 98.144:127.5:155.054
CELL Span12Mux_v1
IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054
CELL Span12Mux_v2
IOPATH I O 130.859:170:206.738 143.944:187:227.412
CELL Span12Mux_v3
IOPATH I O 137.402:178.5:217.075 157.03:204:248.086
CELL Span12Mux_v4
IOPATH I O 170.116:221:268.76 196.288:255:310.108
CELL Span12Mux_v5
IOPATH I O 222.46:289:351.455 248.631:323:392.803
CELL Span12Mux_v6
IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814
CELL Span12Mux_v7
IOPATH I O 261.717:340:413.477 294.432:382.5:465.161
CELL Span12Mux_v8
IOPATH I O 333.689:433.5:527.183 366.404:476:578.868
CELL Span12Mux_v9
IOPATH I O 353.318:459:558.194 392.576:510:620.215
CELL Span12Mux_v10
IOPATH I O 366.404:476:578.868 405.662:527:640.889
CELL Span12Mux_v11
IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9
CELL Span12Mux_v12
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
CELL SRMux
IOPATH I O 431.833:561:682.237 333.689:433.5:527.183

93
icefuzz/tmedges_8k.txt → icefuzz/tmedges.txt
View File

@ -2,6 +2,8 @@ CEMux.O LogicCell40.ce
CEMux.O PRE_IO.CLOCKENABLE
CEMux.O SB_RAM40_4K.RCLKE
CEMux.O SB_RAM40_4K.WCLKE
CascadeBuf.O CascadeMux.I
CascadeMux.O CascadeBuf.I
CascadeMux.O LogicCell40.in2
CascadeMux.O SB_RAM40_4K.RADDR[0]
CascadeMux.O SB_RAM40_4K.RADDR[10]
@ -241,6 +243,7 @@ PLL40.PLLOUTCORE Odrv4.I
PLL40.PLLOUTGLOBAL GlobalMux.I
PLL40.SDO LocalMux.I
PLL40_2.LOCK LocalMux.I
PLL40_2.PLLOUTCOREA LocalMux.I
PLL40_2.PLLOUTCOREA Odrv12.I
PLL40_2.PLLOUTCOREA Odrv4.I
PLL40_2.PLLOUTCOREB LocalMux.I
@ -250,6 +253,7 @@ PLL40_2.PLLOUTGLOBALA GlobalMux.I
PLL40_2.PLLOUTGLOBALB GlobalMux.I
PLL40_2.SDO LocalMux.I
PLL40_2F.LOCK LocalMux.I
PLL40_2F.PLLOUTCOREA LocalMux.I
PLL40_2F.PLLOUTCOREA Odrv12.I
PLL40_2F.PLLOUTCOREA Odrv4.I
PLL40_2F.PLLOUTCOREB LocalMux.I
@ -270,13 +274,17 @@ PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
SB_PLL40_2F_CORE.LOCK LocalMux.I
SB_PLL40_2F_CORE.PLLOUTCOREA LocalMux.I
SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I
SB_PLL40_2F_CORE.PLLOUTCOREA Odrv4.I
SB_PLL40_2F_CORE.PLLOUTCOREB LocalMux.I
SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I
SB_PLL40_2F_CORE.PLLOUTCOREB Odrv4.I
SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I
SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I
SB_PLL40_2F_CORE.SDO LocalMux.I
SB_PLL40_CORE.LOCK LocalMux.I
SB_PLL40_CORE.PLLOUTCORE LocalMux.I
SB_PLL40_CORE.PLLOUTCORE Odrv12.I
SB_PLL40_CORE.PLLOUTCORE Odrv4.I
SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I
SB_PLL40_CORE.SDO LocalMux.I
SB_RAM40_4K.RDATA[0] LocalMux.I
@ -373,6 +381,8 @@ Span12Mux_h.O Span12Mux_v.I
Span12Mux_s0_h.O LocalMux.I
Span12Mux_s0_h.O Sp12to4.I
Span12Mux_s0_h.O Span12Mux_h.I
Span12Mux_s0_h.O Span12Mux_s11_h.I
Span12Mux_s0_h.O Span12Mux_s1_v.I
Span12Mux_s0_h.O Span12Mux_v.I
Span12Mux_s0_v.O LocalMux.I
Span12Mux_s0_v.O Sp12to4.I
@ -383,7 +393,9 @@ Span12Mux_s10_h.O Sp12to4.I
Span12Mux_s10_h.O Span12Mux_h.I
Span12Mux_s10_h.O Span12Mux_s10_v.I
Span12Mux_s10_h.O Span12Mux_s11_v.I
Span12Mux_s10_h.O Span12Mux_s2_v.I
Span12Mux_s10_h.O Span12Mux_s4_v.I
Span12Mux_s10_h.O Span12Mux_s5_v.I
Span12Mux_s10_h.O Span12Mux_s6_v.I
Span12Mux_s10_h.O Span12Mux_s8_v.I
Span12Mux_s10_h.O Span12Mux_s9_v.I
@ -392,6 +404,7 @@ Span12Mux_s10_v.O LocalMux.I
Span12Mux_s10_v.O Sp12to4.I
Span12Mux_s10_v.O Span12Mux_h.I
Span12Mux_s10_v.O Span12Mux_s10_h.I
Span12Mux_s10_v.O Span12Mux_s5_v.I
Span12Mux_s10_v.O Span12Mux_s7_h.I
Span12Mux_s10_v.O Span12Mux_s8_h.I
Span12Mux_s10_v.O Span12Mux_s9_h.I
@ -399,6 +412,7 @@ Span12Mux_s10_v.O Span12Mux_v.I
Span12Mux_s11_h.O LocalMux.I
Span12Mux_s11_h.O Sp12to4.I
Span12Mux_s11_h.O Span12Mux_h.I
Span12Mux_s11_h.O Span12Mux_s0_h.I
Span12Mux_s11_h.O Span12Mux_s10_v.I
Span12Mux_s11_h.O Span12Mux_s11_v.I
Span12Mux_s11_h.O Span12Mux_s6_v.I
@ -407,12 +421,14 @@ Span12Mux_s11_h.O Span12Mux_v.I
Span12Mux_s11_v.O LocalMux.I
Span12Mux_s11_v.O Sp12to4.I
Span12Mux_s11_v.O Span12Mux_h.I
Span12Mux_s11_v.O Span12Mux_s4_v.I
Span12Mux_s11_v.O Span12Mux_s8_h.I
Span12Mux_s11_v.O Span12Mux_s9_h.I
Span12Mux_s11_v.O Span12Mux_v.I
Span12Mux_s1_h.O LocalMux.I
Span12Mux_s1_h.O Sp12to4.I
Span12Mux_s1_h.O Span12Mux_h.I
Span12Mux_s1_h.O Span12Mux_s10_h.I
Span12Mux_s1_h.O Span12Mux_s3_v.I
Span12Mux_s1_h.O Span12Mux_s6_v.I
Span12Mux_s1_h.O Span12Mux_s9_v.I
@ -423,8 +439,16 @@ Span12Mux_s1_v.O Span12Mux_v.I
Span12Mux_s2_h.O LocalMux.I
Span12Mux_s2_h.O Sp12to4.I
Span12Mux_s2_h.O Span12Mux_h.I
Span12Mux_s2_h.O Span12Mux_s0_v.I
Span12Mux_s2_h.O Span12Mux_s10_v.I
Span12Mux_s2_h.O Span12Mux_s11_v.I
Span12Mux_s2_h.O Span12Mux_s1_v.I
Span12Mux_s2_h.O Span12Mux_s2_v.I
Span12Mux_s2_h.O Span12Mux_s3_v.I
Span12Mux_s2_h.O Span12Mux_s4_v.I
Span12Mux_s2_h.O Span12Mux_s6_v.I
Span12Mux_s2_h.O Span12Mux_s8_v.I
Span12Mux_s2_h.O Span12Mux_s9_h.I
Span12Mux_s2_h.O Span12Mux_s9_v.I
Span12Mux_s2_h.O Span12Mux_v.I
Span12Mux_s2_v.O LocalMux.I
@ -432,40 +456,78 @@ Span12Mux_s2_v.O Sp12to4.I
Span12Mux_s2_v.O Span12Mux_h.I
Span12Mux_s2_v.O Span12Mux_s2_h.I
Span12Mux_s2_v.O Span12Mux_s5_h.I
Span12Mux_s2_v.O Span12Mux_s9_h.I
Span12Mux_s2_v.O Span12Mux_v.I
Span12Mux_s3_h.O LocalMux.I
Span12Mux_s3_h.O Sp12to4.I
Span12Mux_s3_h.O Span12Mux_h.I
Span12Mux_s3_h.O Span12Mux_s10_v.I
Span12Mux_s3_h.O Span12Mux_s11_v.I
Span12Mux_s3_h.O Span12Mux_s1_v.I
Span12Mux_s3_h.O Span12Mux_s2_v.I
Span12Mux_s3_h.O Span12Mux_s4_v.I
Span12Mux_s3_h.O Span12Mux_s6_v.I
Span12Mux_s3_h.O Span12Mux_s7_v.I
Span12Mux_s3_h.O Span12Mux_s8_h.I
Span12Mux_s3_h.O Span12Mux_s8_v.I
Span12Mux_s3_h.O Span12Mux_s9_v.I
Span12Mux_s3_h.O Span12Mux_v.I
Span12Mux_s3_v.O LocalMux.I
Span12Mux_s3_v.O Sp12to4.I
Span12Mux_s3_v.O Span12Mux_h.I
Span12Mux_s3_v.O Span12Mux_s8_h.I
Span12Mux_s3_v.O Span12Mux_v.I
Span12Mux_s4_h.O LocalMux.I
Span12Mux_s4_h.O Sp12to4.I
Span12Mux_s4_h.O Span12Mux_h.I
Span12Mux_s4_h.O Span12Mux_s2_v.I
Span12Mux_s4_h.O Span12Mux_s3_v.I
Span12Mux_s4_h.O Span12Mux_s4_v.I
Span12Mux_s4_h.O Span12Mux_s6_v.I
Span12Mux_s4_h.O Span12Mux_s7_h.I
Span12Mux_s4_h.O Span12Mux_s7_v.I
Span12Mux_s4_h.O Span12Mux_s8_v.I
Span12Mux_s4_h.O Span12Mux_v.I
Span12Mux_s4_v.O LocalMux.I
Span12Mux_s4_v.O Sp12to4.I
Span12Mux_s4_v.O Span12Mux_h.I
Span12Mux_s4_v.O Span12Mux_s10_h.I
Span12Mux_s4_v.O Span12Mux_s11_h.I
Span12Mux_s4_v.O Span12Mux_s11_v.I
Span12Mux_s4_v.O Span12Mux_s2_h.I
Span12Mux_s4_v.O Span12Mux_s8_h.I
Span12Mux_s4_v.O Span12Mux_v.I
Span12Mux_s5_h.O LocalMux.I
Span12Mux_s5_h.O Sp12to4.I
Span12Mux_s5_h.O Span12Mux_h.I
Span12Mux_s5_h.O Span12Mux_s10_v.I
Span12Mux_s5_h.O Span12Mux_s11_v.I
Span12Mux_s5_h.O Span12Mux_s6_h.I
Span12Mux_s5_h.O Span12Mux_s7_v.I
Span12Mux_s5_h.O Span12Mux_s8_v.I
Span12Mux_s5_h.O Span12Mux_s9_v.I
Span12Mux_s5_h.O Span12Mux_v.I
Span12Mux_s5_v.O LocalMux.I
Span12Mux_s5_v.O Sp12to4.I
Span12Mux_s5_v.O Span12Mux_h.I
Span12Mux_s5_v.O Span12Mux_s10_h.I
Span12Mux_s5_v.O Span12Mux_s10_v.I
Span12Mux_s5_v.O Span12Mux_s5_h.I
Span12Mux_s5_v.O Span12Mux_s8_h.I
Span12Mux_s5_v.O Span12Mux_v.I
Span12Mux_s6_h.O LocalMux.I
Span12Mux_s6_h.O Sp12to4.I
Span12Mux_s6_h.O Span12Mux_h.I
Span12Mux_s6_h.O Span12Mux_s0_v.I
Span12Mux_s6_h.O Span12Mux_s10_v.I
Span12Mux_s6_h.O Span12Mux_s11_v.I
Span12Mux_s6_h.O Span12Mux_s3_v.I
Span12Mux_s6_h.O Span12Mux_s5_h.I
Span12Mux_s6_h.O Span12Mux_s5_v.I
Span12Mux_s6_h.O Span12Mux_s6_v.I
Span12Mux_s6_h.O Span12Mux_s7_v.I
Span12Mux_s6_h.O Span12Mux_s8_v.I
Span12Mux_s6_h.O Span12Mux_s9_v.I
Span12Mux_s6_h.O Span12Mux_v.I
Span12Mux_s6_v.O LocalMux.I
Span12Mux_s6_v.O Sp12to4.I
@ -475,21 +537,31 @@ Span12Mux_s6_v.O Span12Mux_s5_h.I
Span12Mux_s6_v.O Span12Mux_s7_h.I
Span12Mux_s6_v.O Span12Mux_s8_h.I
Span12Mux_s6_v.O Span12Mux_s9_h.I
Span12Mux_s6_v.O Span12Mux_s9_v.I
Span12Mux_s6_v.O Span12Mux_v.I
Span12Mux_s7_h.O LocalMux.I
Span12Mux_s7_h.O Sp12to4.I
Span12Mux_s7_h.O Span12Mux_h.I
Span12Mux_s7_h.O Span12Mux_s10_v.I
Span12Mux_s7_h.O Span12Mux_s11_v.I
Span12Mux_s7_h.O Span12Mux_s1_v.I
Span12Mux_s7_h.O Span12Mux_s4_h.I
Span12Mux_s7_h.O Span12Mux_s4_v.I
Span12Mux_s7_h.O Span12Mux_s5_v.I
Span12Mux_s7_h.O Span12Mux_s6_v.I
Span12Mux_s7_h.O Span12Mux_s7_v.I
Span12Mux_s7_h.O Span12Mux_s8_v.I
Span12Mux_s7_h.O Span12Mux_s9_v.I
Span12Mux_s7_h.O Span12Mux_v.I
Span12Mux_s7_v.O LocalMux.I
Span12Mux_s7_v.O Sp12to4.I
Span12Mux_s7_v.O Span12Mux_h.I
Span12Mux_s7_v.O Span12Mux_s10_h.I
Span12Mux_s7_v.O Span12Mux_s11_h.I
Span12Mux_s7_v.O Span12Mux_s6_h.I
Span12Mux_s7_v.O Span12Mux_s7_h.I
Span12Mux_s7_v.O Span12Mux_s8_h.I
Span12Mux_s7_v.O Span12Mux_s8_v.I
Span12Mux_s7_v.O Span12Mux_s9_h.I
Span12Mux_s7_v.O Span12Mux_v.I
Span12Mux_s8_h.O LocalMux.I
@ -497,6 +569,9 @@ Span12Mux_s8_h.O Sp12to4.I
Span12Mux_s8_h.O Span12Mux_h.I
Span12Mux_s8_h.O Span12Mux_s10_v.I
Span12Mux_s8_h.O Span12Mux_s11_v.I
Span12Mux_s8_h.O Span12Mux_s2_v.I
Span12Mux_s8_h.O Span12Mux_s3_h.I
Span12Mux_s8_h.O Span12Mux_s3_v.I
Span12Mux_s8_h.O Span12Mux_s4_v.I
Span12Mux_s8_h.O Span12Mux_s5_v.I
Span12Mux_s8_h.O Span12Mux_s6_v.I
@ -509,14 +584,20 @@ Span12Mux_s8_v.O Sp12to4.I
Span12Mux_s8_v.O Span12Mux_h.I
Span12Mux_s8_v.O Span12Mux_s10_h.I
Span12Mux_s8_v.O Span12Mux_s11_h.I
Span12Mux_s8_v.O Span12Mux_s2_h.I
Span12Mux_s8_v.O Span12Mux_s7_h.I
Span12Mux_s8_v.O Span12Mux_s7_v.I
Span12Mux_s8_v.O Span12Mux_s8_h.I
Span12Mux_s8_v.O Span12Mux_v.I
Span12Mux_s9_h.O LocalMux.I
Span12Mux_s9_h.O Sp12to4.I
Span12Mux_s9_h.O Span12Mux_h.I
Span12Mux_s9_h.O Span12Mux_s0_v.I
Span12Mux_s9_h.O Span12Mux_s10_v.I
Span12Mux_s9_h.O Span12Mux_s11_v.I
Span12Mux_s9_h.O Span12Mux_s1_v.I
Span12Mux_s9_h.O Span12Mux_s2_h.I
Span12Mux_s9_h.O Span12Mux_s2_v.I
Span12Mux_s9_h.O Span12Mux_s4_v.I
Span12Mux_s9_h.O Span12Mux_s5_v.I
Span12Mux_s9_h.O Span12Mux_s8_v.I
@ -527,6 +608,8 @@ Span12Mux_s9_v.O Sp12to4.I
Span12Mux_s9_v.O Span12Mux_h.I
Span12Mux_s9_v.O Span12Mux_s11_h.I
Span12Mux_s9_v.O Span12Mux_s5_h.I
Span12Mux_s9_v.O Span12Mux_s6_v.I
Span12Mux_s9_v.O Span12Mux_s7_h.I
Span12Mux_s9_v.O Span12Mux_v.I
Span12Mux_v.O LocalMux.I
Span12Mux_v.O Sp12to4.I
@ -573,14 +656,20 @@ Span4Mux_s0_h.O Span4Mux_h.I
Span4Mux_s0_h.O Span4Mux_s0_v.I
Span4Mux_s0_h.O Span4Mux_s1_v.I
Span4Mux_s0_h.O Span4Mux_s2_v.I
Span4Mux_s0_h.O Span4Mux_s3_v.I
Span4Mux_s0_h.O Span4Mux_v.I
Span4Mux_s0_v.O IoSpan4Mux.I
Span4Mux_s0_v.O LocalMux.I
Span4Mux_s0_v.O Span4Mux_h.I
Span4Mux_s0_v.O Span4Mux_s0_h.I
Span4Mux_s0_v.O Span4Mux_s1_h.I
Span4Mux_s0_v.O Span4Mux_s2_h.I
Span4Mux_s0_v.O Span4Mux_s3_h.I
Span4Mux_s0_v.O Span4Mux_v.I
Span4Mux_s1_h.O IoSpan4Mux.I
Span4Mux_s1_h.O LocalMux.I
Span4Mux_s1_h.O Span4Mux_h.I
Span4Mux_s1_h.O Span4Mux_s0_v.I
Span4Mux_s1_h.O Span4Mux_s1_v.I
Span4Mux_s1_h.O Span4Mux_s2_v.I
Span4Mux_s1_h.O Span4Mux_s3_v.I
@ -596,6 +685,7 @@ Span4Mux_s1_v.O Span4Mux_v.I
Span4Mux_s2_h.O IoSpan4Mux.I
Span4Mux_s2_h.O LocalMux.I
Span4Mux_s2_h.O Span4Mux_h.I
Span4Mux_s2_h.O Span4Mux_s0_v.I
Span4Mux_s2_h.O Span4Mux_s1_v.I
Span4Mux_s2_h.O Span4Mux_s2_v.I
Span4Mux_s2_h.O Span4Mux_s3_v.I
@ -603,6 +693,7 @@ Span4Mux_s2_h.O Span4Mux_v.I
Span4Mux_s2_v.O IoSpan4Mux.I
Span4Mux_s2_v.O LocalMux.I
Span4Mux_s2_v.O Span4Mux_h.I
Span4Mux_s2_v.O Span4Mux_s0_h.I
Span4Mux_s2_v.O Span4Mux_s1_h.I
Span4Mux_s2_v.O Span4Mux_s2_h.I
Span4Mux_s2_v.O Span4Mux_s3_h.I
@ -611,12 +702,14 @@ Span4Mux_s3_h.O IoSpan4Mux.I
Span4Mux_s3_h.O LocalMux.I
Span4Mux_s3_h.O Span4Mux_h.I
Span4Mux_s3_h.O Span4Mux_s0_v.I
Span4Mux_s3_h.O Span4Mux_s1_v.I
Span4Mux_s3_h.O Span4Mux_s2_v.I
Span4Mux_s3_h.O Span4Mux_s3_v.I
Span4Mux_s3_h.O Span4Mux_v.I
Span4Mux_s3_v.O IoSpan4Mux.I
Span4Mux_s3_v.O LocalMux.I
Span4Mux_s3_v.O Span4Mux_h.I
Span4Mux_s3_v.O Span4Mux_s0_h.I
Span4Mux_s3_v.O Span4Mux_s1_h.I
Span4Mux_s3_v.O Span4Mux_s2_h.I
Span4Mux_s3_v.O Span4Mux_s3_h.I

613
icefuzz/tmedges_1k.txt
View File

@ -1,613 +0,0 @@
CEMux.O LogicCell40.ce
CEMux.O PRE_IO.CLOCKENABLE
CEMux.O SB_RAM40_4K.RCLKE
CEMux.O SB_RAM40_4K.WCLKE
CascadeMux.O LogicCell40.in2
CascadeMux.O SB_RAM40_4K.RADDR[0]
CascadeMux.O SB_RAM40_4K.RADDR[10]
CascadeMux.O SB_RAM40_4K.RADDR[1]
CascadeMux.O SB_RAM40_4K.RADDR[2]
CascadeMux.O SB_RAM40_4K.RADDR[3]
CascadeMux.O SB_RAM40_4K.RADDR[4]
CascadeMux.O SB_RAM40_4K.RADDR[5]
CascadeMux.O SB_RAM40_4K.RADDR[6]
CascadeMux.O SB_RAM40_4K.RADDR[7]
CascadeMux.O SB_RAM40_4K.RADDR[8]
CascadeMux.O SB_RAM40_4K.RADDR[9]
CascadeMux.O SB_RAM40_4K.WADDR[0]
CascadeMux.O SB_RAM40_4K.WADDR[10]
CascadeMux.O SB_RAM40_4K.WADDR[1]
CascadeMux.O SB_RAM40_4K.WADDR[2]
CascadeMux.O SB_RAM40_4K.WADDR[3]
CascadeMux.O SB_RAM40_4K.WADDR[4]
CascadeMux.O SB_RAM40_4K.WADDR[5]
CascadeMux.O SB_RAM40_4K.WADDR[6]
CascadeMux.O SB_RAM40_4K.WADDR[7]
CascadeMux.O SB_RAM40_4K.WADDR[8]
CascadeMux.O SB_RAM40_4K.WADDR[9]
ClkMux.O INV.I
ClkMux.O LogicCell40.clk
ClkMux.O PRE_IO.INPUTCLK
ClkMux.O PRE_IO.OUTPUTCLK
ClkMux.O SB_RAM40_4K.RCLK
ClkMux.O SB_RAM40_4K.WCLK
GND.Y LogicCell40.carryin
GND.Y LogicCell40.clk
GND.Y LogicCell40.in0
GND.Y LogicCell40.in1
GND.Y LogicCell40.in2
GND.Y LogicCell40.in3
GND.Y LogicCell40.sr
GND.Y PRE_IO.DOUT0
GND.Y SB_RAM40_4K.WCLK
Glb2LocalMux.O LocalMux.I
GlobalMux.O CEMux.I
GlobalMux.O ClkMux.I
GlobalMux.O Glb2LocalMux.I
GlobalMux.O SRMux.I
ICE_CARRY_IN_MUX.carryinitout InMux.I
ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin
ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
INV.O LogicCell40.clk
INV.O SB_RAM40_4K.RCLK
INV.O SB_RAM40_4K.WCLK
IO_PAD.DOUT PLL40.PLLIN
IO_PAD.DOUT PLL40_2.PLLIN
IO_PAD.DOUT PLL40_2F.PLLIN
IO_PAD.DOUT PRE_IO.PADIN
IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER
IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN
InMux.O CascadeMux.I
InMux.O LogicCell40.in0
InMux.O LogicCell40.in1
InMux.O LogicCell40.in3
InMux.O SB_RAM40_4K.MASK[0]
InMux.O SB_RAM40_4K.MASK[10]
InMux.O SB_RAM40_4K.MASK[11]
InMux.O SB_RAM40_4K.MASK[12]
InMux.O SB_RAM40_4K.MASK[13]
InMux.O SB_RAM40_4K.MASK[14]
InMux.O SB_RAM40_4K.MASK[15]
InMux.O SB_RAM40_4K.MASK[1]
InMux.O SB_RAM40_4K.MASK[2]
InMux.O SB_RAM40_4K.MASK[3]
InMux.O SB_RAM40_4K.MASK[4]
InMux.O SB_RAM40_4K.MASK[5]
InMux.O SB_RAM40_4K.MASK[6]
InMux.O SB_RAM40_4K.MASK[7]
InMux.O SB_RAM40_4K.MASK[8]
InMux.O SB_RAM40_4K.MASK[9]
InMux.O SB_RAM40_4K.WDATA[0]
InMux.O SB_RAM40_4K.WDATA[10]
InMux.O SB_RAM40_4K.WDATA[11]
InMux.O SB_RAM40_4K.WDATA[12]
InMux.O SB_RAM40_4K.WDATA[13]
InMux.O SB_RAM40_4K.WDATA[14]
InMux.O SB_RAM40_4K.WDATA[15]
InMux.O SB_RAM40_4K.WDATA[1]
InMux.O SB_RAM40_4K.WDATA[2]
InMux.O SB_RAM40_4K.WDATA[3]
InMux.O SB_RAM40_4K.WDATA[4]
InMux.O SB_RAM40_4K.WDATA[5]
InMux.O SB_RAM40_4K.WDATA[6]
InMux.O SB_RAM40_4K.WDATA[7]
InMux.O SB_RAM40_4K.WDATA[8]
InMux.O SB_RAM40_4K.WDATA[9]
IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER
IoInMux.O PLL40.BYPASS
IoInMux.O PLL40.DYNAMICDELAY[0]
IoInMux.O PLL40.DYNAMICDELAY[1]
IoInMux.O PLL40.DYNAMICDELAY[2]
IoInMux.O PLL40.DYNAMICDELAY[3]
IoInMux.O PLL40.DYNAMICDELAY[4]
IoInMux.O PLL40.DYNAMICDELAY[5]
IoInMux.O PLL40.DYNAMICDELAY[6]
IoInMux.O PLL40.DYNAMICDELAY[7]
IoInMux.O PLL40.EXTFEEDBACK
IoInMux.O PLL40.LATCHINPUTVALUE
IoInMux.O PLL40.RESETB
IoInMux.O PLL40.SCLK
IoInMux.O PLL40.SDI
IoInMux.O PLL40_2.BYPASS
IoInMux.O PLL40_2.DYNAMICDELAY[0]
IoInMux.O PLL40_2.DYNAMICDELAY[1]
IoInMux.O PLL40_2.DYNAMICDELAY[2]
IoInMux.O PLL40_2.DYNAMICDELAY[3]
IoInMux.O PLL40_2.DYNAMICDELAY[4]
IoInMux.O PLL40_2.DYNAMICDELAY[5]
IoInMux.O PLL40_2.DYNAMICDELAY[6]
IoInMux.O PLL40_2.DYNAMICDELAY[7]
IoInMux.O PLL40_2.EXTFEEDBACK
IoInMux.O PLL40_2.LATCHINPUTVALUE
IoInMux.O PLL40_2.RESETB
IoInMux.O PLL40_2.SCLK
IoInMux.O PLL40_2.SDI
IoInMux.O PLL40_2F.BYPASS
IoInMux.O PLL40_2F.DYNAMICDELAY[0]
IoInMux.O PLL40_2F.DYNAMICDELAY[1]
IoInMux.O PLL40_2F.DYNAMICDELAY[2]
IoInMux.O PLL40_2F.DYNAMICDELAY[3]
IoInMux.O PLL40_2F.DYNAMICDELAY[4]
IoInMux.O PLL40_2F.DYNAMICDELAY[5]
IoInMux.O PLL40_2F.DYNAMICDELAY[6]
IoInMux.O PLL40_2F.DYNAMICDELAY[7]
IoInMux.O PLL40_2F.EXTFEEDBACK
IoInMux.O PLL40_2F.LATCHINPUTVALUE
IoInMux.O PLL40_2F.RESETB
IoInMux.O PLL40_2F.SCLK
IoInMux.O PLL40_2F.SDI
IoInMux.O PRE_IO.DOUT0
IoInMux.O PRE_IO.DOUT1
IoInMux.O PRE_IO.LATCHINPUTVALUE
IoInMux.O PRE_IO.OUTPUTENABLE
IoInMux.O SB_PLL40_2F_CORE.BYPASS
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[0]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[1]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[2]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[3]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[4]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[5]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[6]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[7]
IoInMux.O SB_PLL40_2F_CORE.EXTFEEDBACK
IoInMux.O SB_PLL40_2F_CORE.LATCHINPUTVALUE
IoInMux.O SB_PLL40_2F_CORE.REFERENCECLK
IoInMux.O SB_PLL40_2F_CORE.RESETB
IoInMux.O SB_PLL40_2F_CORE.SCLK
IoInMux.O SB_PLL40_2F_CORE.SDI
IoInMux.O SB_PLL40_CORE.BYPASS
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[0]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[1]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[2]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[3]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[4]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[5]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[6]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[7]
IoInMux.O SB_PLL40_CORE.EXTFEEDBACK
IoInMux.O SB_PLL40_CORE.LATCHINPUTVALUE
IoInMux.O SB_PLL40_CORE.REFERENCECLK
IoInMux.O SB_PLL40_CORE.RESETB
IoInMux.O SB_PLL40_CORE.SCLK
IoInMux.O SB_PLL40_CORE.SDI
IoSpan4Mux.O IoSpan4Mux.I
IoSpan4Mux.O LocalMux.I
IoSpan4Mux.O Span4Mux_h.I
IoSpan4Mux.O Span4Mux_s0_h.I
IoSpan4Mux.O Span4Mux_s0_v.I
IoSpan4Mux.O Span4Mux_s1_h.I
IoSpan4Mux.O Span4Mux_s1_v.I
IoSpan4Mux.O Span4Mux_s2_h.I
IoSpan4Mux.O Span4Mux_s2_v.I
IoSpan4Mux.O Span4Mux_s3_h.I
IoSpan4Mux.O Span4Mux_s3_v.I
IoSpan4Mux.O Span4Mux_v.I
LocalMux.O CEMux.I
LocalMux.O ClkMux.I
LocalMux.O InMux.I
LocalMux.O IoInMux.I
LocalMux.O SRMux.I
LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin
LogicCell40.carryout InMux.I
LogicCell40.carryout LogicCell40.carryin
LogicCell40.lcout LocalMux.I
LogicCell40.lcout Odrv12.I
LogicCell40.lcout Odrv4.I
LogicCell40.ltout CascadeMux.I
Odrv12.O LocalMux.I
Odrv12.O Sp12to4.I
Odrv12.O Span12Mux_s0_h.I
Odrv12.O Span12Mux_s0_v.I
Odrv12.O Span12Mux_s10_h.I
Odrv12.O Span12Mux_s10_v.I
Odrv12.O Span12Mux_s11_h.I
Odrv12.O Span12Mux_s11_v.I
Odrv12.O Span12Mux_s1_h.I
Odrv12.O Span12Mux_s1_v.I
Odrv12.O Span12Mux_s2_h.I
Odrv12.O Span12Mux_s2_v.I
Odrv12.O Span12Mux_s3_h.I
Odrv12.O Span12Mux_s3_v.I
Odrv12.O Span12Mux_s4_h.I
Odrv12.O Span12Mux_s4_v.I
Odrv12.O Span12Mux_s5_h.I
Odrv12.O Span12Mux_s5_v.I
Odrv12.O Span12Mux_s6_h.I
Odrv12.O Span12Mux_s6_v.I
Odrv12.O Span12Mux_s7_h.I
Odrv12.O Span12Mux_s7_v.I
Odrv12.O Span12Mux_s8_h.I
Odrv12.O Span12Mux_s8_v.I
Odrv12.O Span12Mux_s9_h.I
Odrv12.O Span12Mux_s9_v.I
Odrv12.O Span12Mux_v.I
Odrv4.O IoSpan4Mux.I
Odrv4.O LocalMux.I
Odrv4.O Span4Mux_h.I
Odrv4.O Span4Mux_s0_h.I
Odrv4.O Span4Mux_s0_v.I
Odrv4.O Span4Mux_s1_h.I
Odrv4.O Span4Mux_s1_v.I
Odrv4.O Span4Mux_s2_h.I
Odrv4.O Span4Mux_s2_v.I
Odrv4.O Span4Mux_s3_h.I
Odrv4.O Span4Mux_s3_v.I
Odrv4.O Span4Mux_v.I
PLL40.LOCK LocalMux.I
PLL40.PLLOUTCORE LocalMux.I
PLL40.PLLOUTCORE Odrv12.I
PLL40.PLLOUTCORE Odrv4.I
PLL40.PLLOUTGLOBAL GlobalMux.I
PLL40.SDO LocalMux.I
PLL40_2.LOCK LocalMux.I
PLL40_2.PLLOUTCOREA LocalMux.I
PLL40_2.PLLOUTCOREA Odrv12.I
PLL40_2.PLLOUTCOREA Odrv4.I
PLL40_2.PLLOUTCOREB LocalMux.I
PLL40_2.PLLOUTCOREB Odrv12.I
PLL40_2.PLLOUTCOREB Odrv4.I
PLL40_2.PLLOUTGLOBALA GlobalMux.I
PLL40_2.PLLOUTGLOBALB GlobalMux.I
PLL40_2.SDO LocalMux.I
PLL40_2F.LOCK LocalMux.I
PLL40_2F.PLLOUTCOREA LocalMux.I
PLL40_2F.PLLOUTCOREA Odrv12.I
PLL40_2F.PLLOUTCOREA Odrv4.I
PLL40_2F.PLLOUTCOREB LocalMux.I
PLL40_2F.PLLOUTCOREB Odrv12.I
PLL40_2F.PLLOUTCOREB Odrv4.I
PLL40_2F.PLLOUTGLOBALA GlobalMux.I
PLL40_2F.PLLOUTGLOBALB GlobalMux.I
PLL40_2F.SDO LocalMux.I
PRE_IO.DIN0 LocalMux.I
PRE_IO.DIN0 Odrv12.I
PRE_IO.DIN0 Odrv4.I
PRE_IO.DIN1 LocalMux.I
PRE_IO.DIN1 Odrv12.I
PRE_IO.DIN1 Odrv4.I
PRE_IO.PADOEN IO_PAD.OE
PRE_IO.PADOUT IO_PAD.DIN
PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
SB_PLL40_2F_CORE.LOCK LocalMux.I
SB_PLL40_2F_CORE.PLLOUTCOREA LocalMux.I
SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I
SB_PLL40_2F_CORE.PLLOUTCOREA Odrv4.I
SB_PLL40_2F_CORE.PLLOUTCOREB LocalMux.I
SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I
SB_PLL40_2F_CORE.PLLOUTCOREB Odrv4.I
SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I
SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I
SB_PLL40_2F_CORE.SDO LocalMux.I
SB_PLL40_CORE.LOCK LocalMux.I
SB_PLL40_CORE.PLLOUTCORE LocalMux.I
SB_PLL40_CORE.PLLOUTCORE Odrv12.I
SB_PLL40_CORE.PLLOUTCORE Odrv4.I
SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I
SB_PLL40_CORE.SDO LocalMux.I
SB_RAM40_4K.RDATA[0] LocalMux.I
SB_RAM40_4K.RDATA[0] Odrv12.I
SB_RAM40_4K.RDATA[0] Odrv4.I
SB_RAM40_4K.RDATA[10] LocalMux.I
SB_RAM40_4K.RDATA[10] Odrv12.I
SB_RAM40_4K.RDATA[10] Odrv4.I
SB_RAM40_4K.RDATA[11] LocalMux.I
SB_RAM40_4K.RDATA[11] Odrv12.I
SB_RAM40_4K.RDATA[11] Odrv4.I
SB_RAM40_4K.RDATA[12] LocalMux.I
SB_RAM40_4K.RDATA[12] Odrv12.I
SB_RAM40_4K.RDATA[12] Odrv4.I
SB_RAM40_4K.RDATA[13] LocalMux.I
SB_RAM40_4K.RDATA[13] Odrv12.I
SB_RAM40_4K.RDATA[13] Odrv4.I
SB_RAM40_4K.RDATA[14] LocalMux.I
SB_RAM40_4K.RDATA[14] Odrv12.I
SB_RAM40_4K.RDATA[14] Odrv4.I
SB_RAM40_4K.RDATA[15] LocalMux.I
SB_RAM40_4K.RDATA[15] Odrv12.I
SB_RAM40_4K.RDATA[15] Odrv4.I
SB_RAM40_4K.RDATA[1] LocalMux.I
SB_RAM40_4K.RDATA[1] Odrv12.I
SB_RAM40_4K.RDATA[1] Odrv4.I
SB_RAM40_4K.RDATA[2] LocalMux.I
SB_RAM40_4K.RDATA[2] Odrv12.I
SB_RAM40_4K.RDATA[2] Odrv4.I
SB_RAM40_4K.RDATA[3] LocalMux.I
SB_RAM40_4K.RDATA[3] Odrv12.I
SB_RAM40_4K.RDATA[3] Odrv4.I
SB_RAM40_4K.RDATA[4] LocalMux.I
SB_RAM40_4K.RDATA[4] Odrv12.I
SB_RAM40_4K.RDATA[4] Odrv4.I
SB_RAM40_4K.RDATA[5] LocalMux.I
SB_RAM40_4K.RDATA[5] Odrv12.I
SB_RAM40_4K.RDATA[5] Odrv4.I
SB_RAM40_4K.RDATA[6] LocalMux.I
SB_RAM40_4K.RDATA[6] Odrv12.I
SB_RAM40_4K.RDATA[6] Odrv4.I
SB_RAM40_4K.RDATA[7] LocalMux.I
SB_RAM40_4K.RDATA[7] Odrv12.I
SB_RAM40_4K.RDATA[7] Odrv4.I
SB_RAM40_4K.RDATA[8] LocalMux.I
SB_RAM40_4K.RDATA[8] Odrv12.I
SB_RAM40_4K.RDATA[8] Odrv4.I
SB_RAM40_4K.RDATA[9] LocalMux.I
SB_RAM40_4K.RDATA[9] Odrv12.I
SB_RAM40_4K.RDATA[9] Odrv4.I
SRMux.O LogicCell40.sr
SRMux.O SB_RAM40_4K.RE
SRMux.O SB_RAM40_4K.WE
Sp12to4.O IoSpan4Mux.I
Sp12to4.O LocalMux.I
Sp12to4.O Span4Mux_h.I
Sp12to4.O Span4Mux_s0_h.I
Sp12to4.O Span4Mux_s0_v.I
Sp12to4.O Span4Mux_s1_h.I
Sp12to4.O Span4Mux_s1_v.I
Sp12to4.O Span4Mux_s2_h.I
Sp12to4.O Span4Mux_s2_v.I
Sp12to4.O Span4Mux_s3_h.I
Sp12to4.O Span4Mux_s3_v.I
Sp12to4.O Span4Mux_v.I
Span12Mux_s0_h.O LocalMux.I
Span12Mux_s0_h.O Sp12to4.I
Span12Mux_s0_h.O Span12Mux_s11_h.I
Span12Mux_s0_h.O Span12Mux_s1_v.I
Span12Mux_s0_v.O LocalMux.I
Span12Mux_s0_v.O Sp12to4.I
Span12Mux_s0_v.O Span12Mux_v.I
Span12Mux_s10_h.O LocalMux.I
Span12Mux_s10_h.O Sp12to4.I
Span12Mux_s10_h.O Span12Mux_s2_v.I
Span12Mux_s10_h.O Span12Mux_s5_v.I
Span12Mux_s10_h.O Span12Mux_v.I
Span12Mux_s10_v.O LocalMux.I
Span12Mux_s10_v.O Sp12to4.I
Span12Mux_s10_v.O Span12Mux_s10_h.I
Span12Mux_s10_v.O Span12Mux_s5_v.I
Span12Mux_s10_v.O Span12Mux_s8_h.I
Span12Mux_s11_h.O LocalMux.I
Span12Mux_s11_h.O Sp12to4.I
Span12Mux_s11_h.O Span12Mux_s0_h.I
Span12Mux_s11_v.O LocalMux.I
Span12Mux_s11_v.O Sp12to4.I
Span12Mux_s11_v.O Span12Mux_s4_v.I
Span12Mux_s11_v.O Span12Mux_s8_h.I
Span12Mux_s11_v.O Span12Mux_s9_h.I
Span12Mux_s1_h.O LocalMux.I
Span12Mux_s1_h.O Sp12to4.I
Span12Mux_s1_h.O Span12Mux_s10_h.I
Span12Mux_s1_v.O LocalMux.I
Span12Mux_s1_v.O Sp12to4.I
Span12Mux_s1_v.O Span12Mux_v.I
Span12Mux_s2_h.O LocalMux.I
Span12Mux_s2_h.O Sp12to4.I
Span12Mux_s2_h.O Span12Mux_s0_v.I
Span12Mux_s2_h.O Span12Mux_s10_v.I
Span12Mux_s2_h.O Span12Mux_s11_v.I
Span12Mux_s2_h.O Span12Mux_s1_v.I
Span12Mux_s2_h.O Span12Mux_s2_v.I
Span12Mux_s2_h.O Span12Mux_s4_v.I
Span12Mux_s2_h.O Span12Mux_s6_v.I
Span12Mux_s2_h.O Span12Mux_s8_v.I
Span12Mux_s2_h.O Span12Mux_s9_h.I
Span12Mux_s2_h.O Span12Mux_s9_v.I
Span12Mux_s2_v.O LocalMux.I
Span12Mux_s2_v.O Sp12to4.I
Span12Mux_s2_v.O Span12Mux_s9_h.I
Span12Mux_s3_h.O LocalMux.I
Span12Mux_s3_h.O Sp12to4.I
Span12Mux_s3_h.O Span12Mux_s10_v.I
Span12Mux_s3_h.O Span12Mux_s11_v.I
Span12Mux_s3_h.O Span12Mux_s1_v.I
Span12Mux_s3_h.O Span12Mux_s2_v.I
Span12Mux_s3_h.O Span12Mux_s4_v.I
Span12Mux_s3_h.O Span12Mux_s6_v.I
Span12Mux_s3_h.O Span12Mux_s7_v.I
Span12Mux_s3_h.O Span12Mux_s8_h.I
Span12Mux_s3_h.O Span12Mux_s8_v.I
Span12Mux_s3_h.O Span12Mux_s9_v.I
Span12Mux_s3_h.O Span12Mux_v.I
Span12Mux_s3_v.O LocalMux.I
Span12Mux_s3_v.O Sp12to4.I
Span12Mux_s3_v.O Span12Mux_s8_h.I
Span12Mux_s3_v.O Span12Mux_v.I
Span12Mux_s4_h.O LocalMux.I
Span12Mux_s4_h.O Sp12to4.I
Span12Mux_s4_h.O Span12Mux_s2_v.I
Span12Mux_s4_h.O Span12Mux_s3_v.I
Span12Mux_s4_h.O Span12Mux_s4_v.I
Span12Mux_s4_h.O Span12Mux_s6_v.I
Span12Mux_s4_h.O Span12Mux_s7_h.I
Span12Mux_s4_h.O Span12Mux_s7_v.I
Span12Mux_s4_h.O Span12Mux_s8_v.I
Span12Mux_s4_v.O LocalMux.I
Span12Mux_s4_v.O Sp12to4.I
Span12Mux_s4_v.O Span12Mux_s10_h.I
Span12Mux_s4_v.O Span12Mux_s11_v.I
Span12Mux_s4_v.O Span12Mux_s2_h.I
Span12Mux_s4_v.O Span12Mux_s8_h.I
Span12Mux_s5_h.O LocalMux.I
Span12Mux_s5_h.O Sp12to4.I
Span12Mux_s5_h.O Span12Mux_s10_v.I
Span12Mux_s5_h.O Span12Mux_s11_v.I
Span12Mux_s5_h.O Span12Mux_s6_h.I
Span12Mux_s5_h.O Span12Mux_s7_v.I
Span12Mux_s5_h.O Span12Mux_s8_v.I
Span12Mux_s5_h.O Span12Mux_s9_v.I
Span12Mux_s5_h.O Span12Mux_v.I
Span12Mux_s5_v.O LocalMux.I
Span12Mux_s5_v.O Sp12to4.I
Span12Mux_s5_v.O Span12Mux_s10_h.I
Span12Mux_s5_v.O Span12Mux_s10_v.I
Span12Mux_s5_v.O Span12Mux_s5_h.I
Span12Mux_s5_v.O Span12Mux_s8_h.I
Span12Mux_s6_h.O LocalMux.I
Span12Mux_s6_h.O Sp12to4.I
Span12Mux_s6_h.O Span12Mux_s0_v.I
Span12Mux_s6_h.O Span12Mux_s11_v.I
Span12Mux_s6_h.O Span12Mux_s3_v.I
Span12Mux_s6_h.O Span12Mux_s5_h.I
Span12Mux_s6_h.O Span12Mux_s5_v.I
Span12Mux_s6_h.O Span12Mux_s7_v.I
Span12Mux_s6_h.O Span12Mux_s8_v.I
Span12Mux_s6_h.O Span12Mux_s9_v.I
Span12Mux_s6_h.O Span12Mux_v.I
Span12Mux_s6_v.O LocalMux.I
Span12Mux_s6_v.O Sp12to4.I
Span12Mux_s6_v.O Span12Mux_s5_h.I
Span12Mux_s6_v.O Span12Mux_s8_h.I
Span12Mux_s6_v.O Span12Mux_s9_v.I
Span12Mux_s7_h.O LocalMux.I
Span12Mux_s7_h.O Sp12to4.I
Span12Mux_s7_h.O Span12Mux_s10_v.I
Span12Mux_s7_h.O Span12Mux_s1_v.I
Span12Mux_s7_h.O Span12Mux_s4_h.I
Span12Mux_s7_h.O Span12Mux_s8_v.I
Span12Mux_s7_h.O Span12Mux_s9_v.I
Span12Mux_s7_h.O Span12Mux_v.I
Span12Mux_s7_v.O LocalMux.I
Span12Mux_s7_v.O Sp12to4.I
Span12Mux_s7_v.O Span12Mux_s10_h.I
Span12Mux_s7_v.O Span12Mux_s11_h.I
Span12Mux_s7_v.O Span12Mux_s6_h.I
Span12Mux_s7_v.O Span12Mux_s7_h.I
Span12Mux_s7_v.O Span12Mux_s8_h.I
Span12Mux_s7_v.O Span12Mux_s8_v.I
Span12Mux_s8_h.O LocalMux.I
Span12Mux_s8_h.O Sp12to4.I
Span12Mux_s8_h.O Span12Mux_s10_v.I
Span12Mux_s8_h.O Span12Mux_s11_v.I
Span12Mux_s8_h.O Span12Mux_s2_v.I
Span12Mux_s8_h.O Span12Mux_s3_h.I
Span12Mux_s8_h.O Span12Mux_s3_v.I
Span12Mux_s8_h.O Span12Mux_s4_v.I
Span12Mux_s8_h.O Span12Mux_s6_v.I
Span12Mux_s8_h.O Span12Mux_s7_v.I
Span12Mux_s8_h.O Span12Mux_s8_v.I
Span12Mux_s8_h.O Span12Mux_s9_v.I
Span12Mux_s8_h.O Span12Mux_v.I
Span12Mux_s8_v.O LocalMux.I
Span12Mux_s8_v.O Sp12to4.I
Span12Mux_s8_v.O Span12Mux_s10_h.I
Span12Mux_s8_v.O Span12Mux_s2_h.I
Span12Mux_s8_v.O Span12Mux_s7_v.I
Span12Mux_s8_v.O Span12Mux_s8_h.I
Span12Mux_s9_h.O LocalMux.I
Span12Mux_s9_h.O Sp12to4.I
Span12Mux_s9_h.O Span12Mux_s0_v.I
Span12Mux_s9_h.O Span12Mux_s10_v.I
Span12Mux_s9_h.O Span12Mux_s1_v.I
Span12Mux_s9_h.O Span12Mux_s2_h.I
Span12Mux_s9_h.O Span12Mux_s2_v.I
Span12Mux_s9_h.O Span12Mux_s4_v.I
Span12Mux_s9_h.O Span12Mux_v.I
Span12Mux_s9_v.O LocalMux.I
Span12Mux_s9_v.O Sp12to4.I
Span12Mux_s9_v.O Span12Mux_s6_v.I
Span12Mux_s9_v.O Span12Mux_s7_h.I
Span12Mux_v.O LocalMux.I
Span12Mux_v.O Sp12to4.I
Span12Mux_v.O Span12Mux_s0_h.I
Span12Mux_v.O Span12Mux_s0_v.I
Span12Mux_v.O Span12Mux_s10_h.I
Span12Mux_v.O Span12Mux_s11_h.I
Span12Mux_v.O Span12Mux_s1_h.I
Span12Mux_v.O Span12Mux_s1_v.I
Span12Mux_v.O Span12Mux_s2_h.I
Span12Mux_v.O Span12Mux_s2_v.I
Span12Mux_v.O Span12Mux_s3_h.I
Span12Mux_v.O Span12Mux_s3_v.I
Span12Mux_v.O Span12Mux_s4_h.I
Span12Mux_v.O Span12Mux_s5_h.I
Span12Mux_v.O Span12Mux_s6_h.I
Span12Mux_v.O Span12Mux_s7_h.I
Span12Mux_v.O Span12Mux_s8_h.I
Span12Mux_v.O Span12Mux_s9_h.I
Span4Mux_h.O LocalMux.I
Span4Mux_h.O Span4Mux_h.I
Span4Mux_h.O Span4Mux_s0_h.I
Span4Mux_h.O Span4Mux_s0_v.I
Span4Mux_h.O Span4Mux_s1_h.I
Span4Mux_h.O Span4Mux_s1_v.I
Span4Mux_h.O Span4Mux_s2_h.I
Span4Mux_h.O Span4Mux_s2_v.I
Span4Mux_h.O Span4Mux_s3_h.I
Span4Mux_h.O Span4Mux_s3_v.I
Span4Mux_h.O Span4Mux_v.I
Span4Mux_s0_h.O IoSpan4Mux.I
Span4Mux_s0_h.O LocalMux.I
Span4Mux_s0_h.O Span4Mux_h.I
Span4Mux_s0_h.O Span4Mux_s0_v.I
Span4Mux_s0_h.O Span4Mux_s1_v.I
Span4Mux_s0_h.O Span4Mux_s2_v.I
Span4Mux_s0_h.O Span4Mux_s3_v.I
Span4Mux_s0_h.O Span4Mux_v.I
Span4Mux_s0_v.O IoSpan4Mux.I
Span4Mux_s0_v.O LocalMux.I
Span4Mux_s0_v.O Span4Mux_h.I
Span4Mux_s0_v.O Span4Mux_s0_h.I
Span4Mux_s0_v.O Span4Mux_s1_h.I
Span4Mux_s0_v.O Span4Mux_s2_h.I
Span4Mux_s0_v.O Span4Mux_s3_h.I
Span4Mux_s0_v.O Span4Mux_v.I
Span4Mux_s1_h.O IoSpan4Mux.I
Span4Mux_s1_h.O LocalMux.I
Span4Mux_s1_h.O Span4Mux_h.I
Span4Mux_s1_h.O Span4Mux_s0_v.I
Span4Mux_s1_h.O Span4Mux_s1_v.I
Span4Mux_s1_h.O Span4Mux_s2_v.I
Span4Mux_s1_h.O Span4Mux_s3_v.I
Span4Mux_s1_h.O Span4Mux_v.I
Span4Mux_s1_v.O IoSpan4Mux.I
Span4Mux_s1_v.O LocalMux.I
Span4Mux_s1_v.O Span4Mux_h.I
Span4Mux_s1_v.O Span4Mux_s0_h.I
Span4Mux_s1_v.O Span4Mux_s1_h.I
Span4Mux_s1_v.O Span4Mux_s2_h.I
Span4Mux_s1_v.O Span4Mux_s3_h.I
Span4Mux_s1_v.O Span4Mux_v.I
Span4Mux_s2_h.O IoSpan4Mux.I
Span4Mux_s2_h.O LocalMux.I
Span4Mux_s2_h.O Span4Mux_h.I
Span4Mux_s2_h.O Span4Mux_s0_v.I
Span4Mux_s2_h.O Span4Mux_s1_v.I
Span4Mux_s2_h.O Span4Mux_s2_v.I
Span4Mux_s2_h.O Span4Mux_s3_v.I
Span4Mux_s2_h.O Span4Mux_v.I
Span4Mux_s2_v.O IoSpan4Mux.I
Span4Mux_s2_v.O LocalMux.I
Span4Mux_s2_v.O Span4Mux_h.I
Span4Mux_s2_v.O Span4Mux_s0_h.I
Span4Mux_s2_v.O Span4Mux_s1_h.I
Span4Mux_s2_v.O Span4Mux_s2_h.I
Span4Mux_s2_v.O Span4Mux_s3_h.I
Span4Mux_s2_v.O Span4Mux_v.I
Span4Mux_s3_h.O IoSpan4Mux.I
Span4Mux_s3_h.O LocalMux.I
Span4Mux_s3_h.O Span4Mux_h.I
Span4Mux_s3_h.O Span4Mux_s0_v.I
Span4Mux_s3_h.O Span4Mux_s1_v.I
Span4Mux_s3_h.O Span4Mux_s2_v.I
Span4Mux_s3_h.O Span4Mux_s3_v.I
Span4Mux_s3_h.O Span4Mux_v.I
Span4Mux_s3_v.O IoSpan4Mux.I
Span4Mux_s3_v.O LocalMux.I
Span4Mux_s3_v.O Span4Mux_h.I
Span4Mux_s3_v.O Span4Mux_s0_h.I
Span4Mux_s3_v.O Span4Mux_s1_h.I
Span4Mux_s3_v.O Span4Mux_s2_h.I
Span4Mux_s3_v.O Span4Mux_s3_h.I
Span4Mux_s3_v.O Span4Mux_v.I
Span4Mux_v.O LocalMux.I
Span4Mux_v.O Span4Mux_h.I
Span4Mux_v.O Span4Mux_s0_h.I
Span4Mux_v.O Span4Mux_s0_v.I
Span4Mux_v.O Span4Mux_s1_h.I
Span4Mux_v.O Span4Mux_s1_v.I
Span4Mux_v.O Span4Mux_s2_h.I
Span4Mux_v.O Span4Mux_s2_v.I
Span4Mux_v.O Span4Mux_s3_h.I
Span4Mux_v.O Span4Mux_s3_v.I
Span4Mux_v.O Span4Mux_v.I
VCC.Y IO_PAD.OE
VCC.Y PRE_IO.CLOCKENABLE
gio2CtrlBuf.O GlobalMux.I

6
icetime/Makefile
View File

@ -8,7 +8,7 @@ icetime: icetime.o
icetime.o: icetime.cc timings.inc
timings.inc: timings.py
timings.inc: timings.py ../icefuzz/timings_*.txt
python3 timings.py > timings.inc.new
mv timings.inc.new timings.inc
@ -26,11 +26,11 @@ uninstall:
test0 test1 test2 test3 test4 test5 test6 test7 test8 test9: icetime
test -f $@_ref.v || python3 mktest.py $@
./icetime -m -P tq144 -p $@.pcf -o $@_out.v $@.asc
./icetime -m -d hx1k -P tq144 -p $@.pcf -o $@_out.v $@.asc
yosys $@.ys
run0 run1 run2 run3 run4 run5 run6 run7 run8 run9: icetime
./icetime -t -P tq144 -p $(subst run,test,$@).pcf $(subst run,test,$@).asc
./icetime -t -d hx1k -P tq144 -p $(subst run,test,$@).pcf $(subst run,test,$@).asc
show0 show1 show2 show3 show4 show5 show6 show7 show8 show9: icetime
bash show.sh $(subst show,test,$@)

49
icetime/icetime.cc
View File

@ -35,7 +35,7 @@ FILE *fin = nullptr, *fout = nullptr, *frpt = nullptr;
bool verbose = false;
bool max_span_hack = false;
std::string config_device, selected_package;
std::string config_device, device_type, selected_package;
std::vector<std::vector<std::string>> config_tile_type;
std::vector<std::vector<std::vector<std::vector<bool>>>> config_bits;
std::map<std::tuple<int, int, int>, std::string> pin_pos;
@ -613,13 +613,19 @@ double get_delay(std::string cell_type, std::string in_port, std::string out_por
if (cell_type == "INTERCONN")
return 0;
if (config_device == "1k")
return get_delay_1k(cell_type, in_port, out_port);
if (device_type == "lp1k")
return get_delay_lp1k(cell_type, in_port, out_port);
if (config_device == "8k")
return get_delay_8k(cell_type, in_port, out_port);
if (device_type == "lp8k")
return get_delay_lp8k(cell_type, in_port, out_port);
fprintf(stderr, "No built-in timing database for '%s' devices!\n", config_device.c_str());
if (device_type == "hx1k")
return get_delay_hx1k(cell_type, in_port, out_port);
if (device_type == "hx8k")
return get_delay_hx8k(cell_type, in_port, out_port);
fprintf(stderr, "No built-in timing database for '%s' devices!\n", device_type.c_str());
exit(1);
}
@ -1777,6 +1783,9 @@ void help(const char *cmd)
printf(" -r <output_file>\n");
printf(" write timing report to the file (instead of stdout)\n");
printf("\n");
printf(" -d lp1k|hx1k|lp8k|hx8k\n");
printf(" select the device type (default = lp variant)\n");
printf("\n");
printf(" -m\n");
printf(" enable max_span_hack for conservative timing estimates\n");
printf("\n");
@ -1803,7 +1812,7 @@ int main(int argc, char **argv)
std::vector<std::string> print_timing_nets;
int opt;
while ((opt = getopt(argc, argv, "p:P:g:o:r:mitT:v")) != -1)
while ((opt = getopt(argc, argv, "p:P:g:o:r:d:mitT:v")) != -1)
{
switch (opt)
{
@ -1836,6 +1845,9 @@ int main(int argc, char **argv)
exit(1);
}
break;
case 'd':
device_type = optarg;
break;
case 'm':
max_span_hack = true;
break;
@ -1869,6 +1881,29 @@ int main(int argc, char **argv)
fflush(stdout);
read_config();
if (device_type.empty()) {
device_type = "lp" + config_device;
printf("// Warning: Missing -d paramter. Assuming '%s' device.\n", device_type.c_str());
}
if (device_type == "lp1k" || device_type == "hx1k") {
if (config_device != "1k")
goto device_chip_mismatch;
} else
if (device_type == "lp8k" || device_type == "hx8k") {
if (config_device != "8k")
goto device_chip_mismatch;
} else {
fprintf(stderr, "Error: Invalid device type '%s'.\n", device_type.c_str());
exit(1);
}
if (0) {
device_chip_mismatch:
printf("// Warning: Device type '%s' and chip '%s' do not match.\n", device_type.c_str(), config_device.c_str());
fflush(stdout);
}
printf("// Reading %s chipdb file..\n", config_device.c_str());
fflush(stdout);
read_chipdb();

8
icetime/timings.py
View File

@ -41,9 +41,7 @@ def timings_to_c(chip, f):
print(" exit(1);")
print("}")
with open("../icefuzz/timings_1k.txt", "r") as f:
timings_to_c("1k", f);
with open("../icefuzz/timings_8k.txt", "r") as f:
timings_to_c("8k", f);
for db in "lp1k lp8k hx1k hx8k".split():
with open("../icefuzz/timings_%s.txt" % db, "r") as f:
timings_to_c(db, f);