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113 Commits

Author SHA1 Message Date
Matt Venn d06a967590 Update Claire's name and fix the reference image in the iceprog help 2025-06-03 11:06:08 +02:00
Miodrag Milanovic 7190770949 Resolve warning with python 3.12 2024-12-11 13:09:43 +01:00
Sylvain Munaut bb519401cd icebox: Add PLL ICEGATE function 
Only tested on UP5k. For others, it was just deduced.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2023-02-01 11:04:27 +01:00
gatecat e23274a9dd icebox: cb121 does have a PLL 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-25 15:52:44 +00:00
Nils Albartus d969c333d0 added I2C and SPI for u4k to database 2020-12-04 16:47:05 +01:00
Sylvain Munaut ce1d811d21 icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5k 
This allows selection of the div-by-5 mode of the PLL.
This bit can't be fuzzed because it's not supported by the lattice
tools at all ...

This only works for sure on the UP5k.

I tested HX8k and it didn't support it, so I'm only adding this on
the known working FPGA.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-06-03 10:45:31 +02:00
David Shah 1cec1328e0 up5k: Fix TOPADDSUB_CARRYSELECT_0 override where it swaps with osc trimming 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-03 12:54:00 +01:00
Simon Schubert 56978cde58 add RGB_DRV/LED_DRV_CUR for u4k 2019-06-10 13:06:11 +02:00
Michael Buesch 2aff52f10a icebox: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch 795e0003f2 icebox: Add helper functions to LRU cache regular expression results 2019-06-08 16:12:16 +02:00
Michael Buesch 5f49bea71c icebox: Use LRU cache for often called function tile_has_net() 2019-06-08 16:12:07 +02:00
Simon Schubert be0bca0230 u4k: add SMCCLK cell location 
icecube uses SMCCLK.CLK to "legalize" output cells.  Unclear what this
is for, but it appears in almost all outputs.
 2019-02-22 22:35:55 +01:00
Simon Schubert d76ac32ec9 iCE40 Ultra = iCE5LP = u4k port 2019-02-22 22:35:55 +01:00
Clifford Wolf 5ab07ed32a
Merge pull request #178 from elmsfu/hlc/add_symbols_support 
hlc: parse '.sym>' to track signal names from HLC to ASC
 2018-10-10 13:46:31 +02:00
Andrew Wygle 9dbc14410f Add support for cm36 and swg25tr lm4k packages. 2018-08-28 08:29:53 -07:00
Elms 542e9ef0f3 icebox: parse '.sym>' HLC to track signal names 2018-07-26 10:12:56 -07:00
David Shah eee9aac2e1 icebox: Allow selecting package in icebox_vlog 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-05-30 11:24:40 +02:00
Andrew Wygle 704348f563 Correct internal global buffers for lm4k 2018-05-13 11:00:40 -07:00
Andrew Wygle a34ef88b8e Added missing ieren entries for lm4k. 
Config SPI pins weren't present in ioctrl_lm4k.sh
 2018-05-13 11:00:26 -07:00
Andrew Wygle 2d571cb728 Support lm4k in icebox_chipdb.py. 2018-05-13 10:58:22 -07:00
Andrew Wygle 9c11606f1d Completed first pass at icebox support for lm4k. 
Needs testing.
 2018-05-12 21:47:09 -07:00
Andrew Wygle f35701f89a [WIP] Added colbuf and gbufin data for LM series 2018-05-12 21:47:09 -07:00
Andrew Wygle da18da271b [WIP] Add partial icebox support for lm4k. 2018-05-12 21:47:09 -07:00
David Shah 4f4409ad86 Add BG121 package variant and update docs 2018-04-02 15:01:45 +01:00
David Shah b024ef49da Add UltraPlus I³C IO to chipdb 2018-02-09 13:42:38 +00:00
David Shah 80dbd67e6c Add RGB driver outputs to chipdb 2018-02-09 09:42:08 +00:00
David Shah 7e587c9b6b Add 5k UWG30 ieren data to db 2018-01-16 15:17:20 +00:00
David Shah a59472812c Remove seperate 5k RAM DB and share with 8k instead 
This should ensure that the 5k RAM routing entries are now complete,
fixing #115
 2018-01-16 15:17:20 +00:00
David Shah 02a986b2f4 Add pinout for 5k UWG30 package 2018-01-16 15:17:20 +00:00
David Shah 77eafa89b4 HFOSC trimming info 2018-01-16 15:17:20 +00:00
David Shah 9e81ac7786 New UltraPlus corner tracing algorithm 2018-01-16 15:17:12 +00:00
David Shah 0932c559a7 Misc routing tweaks 2018-01-16 15:17:12 +00:00
David Shah ec3ad58683 Figure out missing SPI config bits, and add to chipdb 2018-01-16 15:16:44 +00:00
David Shah 70d295212a Chipdb fix for hard IP 2017-11-26 11:46:38 +00:00
David Shah 6f2d9def4f Add UltraPlus IP to chipdb 2017-11-24 18:49:28 +00:00
David Shah bd6cf518f3 Begin I2C/SPI IP reverse engineering 2017-11-23 19:45:27 +00:00
David Shah da7a2a9d0d Fix whitespace and a couple of typos 2017-11-20 09:43:54 +00:00
David Shah b059f37b50 Add all cf_bits and pullup strength notes 2017-11-18 15:38:14 +00:00
David Shah 095b8404e8 Remove non-existing routing resources (5k) 2017-11-17 15:10:04 +00:00
David Shah afcc653b78 Add support for UltraPlus SPRAM 2017-11-17 15:10:04 +00:00
David Shah c71db50a27 Add UltraPlus LED driver support and demo 2017-11-17 15:09:58 +00:00
David Shah e7d22f2277 UltraPlus Internal Oscillator support 2017-11-17 15:09:58 +00:00
David Shah cdf6883639 UltraPlus DSPs working 2017-11-17 15:09:51 +00:00
David Shah 8f9eba3fe3 Add new tile types and MAC16s to chipdb 2017-11-17 15:09:41 +00:00
David Shah c9160c77dc Tidy up some of the icebox changes 2017-11-17 15:09:40 +00:00
David Shah 2f962ac92e Fix 5k corner routing, and reverse engineer SPRAM 2017-11-17 15:09:17 +00:00
David Shah 88eebff7db Start UltraPlus DSP documentation 2017-11-17 15:08:47 +00:00
David Shah 94aa596cb1 Trace DSP routing 2017-11-17 15:08:25 +00:00
David Shah c69b87d593 Fix 5k gbin configuration 2017-11-06 16:14:41 +00:00
David Shah 1c56e56032 Fix 5k padin_glb_netwk bits 2017-11-05 16:32:58 +00:00