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icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5k 

This allows selection of the div-by-5 mode of the PLL.
This bit can't be fuzzed because it's not supported by the lattice
tools at all ...

This only works for sure on the UP5k.

I tested HX8k and it didn't support it, so I'm only adding this on
the known working FPGA.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2020-06-02 10:33:21 +02:00
parent cd2610e0fa
commit ce1d811d21
1 changed files with 2 additions and 1 deletions
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3
icebox/icebox.py
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@ -1954,7 +1954,8 @@ pllinfo_db = {
"PLLOUT_SELECT_B_1": (12, 31, "PLLCONFIG_3"),
# Numeric Parameters
"SHIFTREG_DIV_MODE": (12, 31, "PLLCONFIG_4"),
"SHIFTREG_DIV_MODE_0": (12, 31, "PLLCONFIG_4"),
"SHIFTREG_DIV_MODE_1": (14, 31, "PLLCONFIG_6"),
"FDA_FEEDBACK_0": (12, 31, "PLLCONFIG_9"),
"FDA_FEEDBACK_1": (13, 31, "PLLCONFIG_1"),
"FDA_FEEDBACK_2": (13, 31, "PLLCONFIG_2"),