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Start UltraPlus DSP documentation
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David Shah
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<!DOCTYPE html>
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<html><head><meta charset="UTF-8">
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<style>
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.ctab {
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margin-left: auto;
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margin-right: auto;
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border: 1px solid gray;
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}
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.ctab td, .ctab th {
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padding: 3px;
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border: 1px solid gray;
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}
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.ctab td {
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font-family:monospace;
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}
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</style>
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<title>Project IceStorm – UltraPlus Features Documentation</title>
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</head><body>
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<h1>Project IceStorm – UltraPlus Features Documentation</h1>
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<p>
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<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
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FPGAs and providing simple tools for analyzing and creating bitstream files.
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This is work in progress.</i>
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</p>
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<p>The ice40 UltraPlus devices have a number of new features compared to the older LP/HX series
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devices, in particular:
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<ul>
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<li>Internal DSP units, capable of 16-bit multiply and 32-bit accumulate.</li>
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<li>1Mbit of extra single-ported RAM, in addition to the usual BRAM</li>
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<li>Internal hard IP cores for I2C and SPI</li>
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<li>2 internal oscillators, 48MHz (with divider) and 10kHz</li>
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<li>24mA constant current LED ouputs and PWM hard IP</li>
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</ul>
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In order to implement these new features, a significant architecural change has been made: the
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left and right sides of the device are no longer IO, but instead DSP and IPConnect tiles.
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</p>
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<h2>DSP Tiles</h2>
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<p>Each MAC16 DSP comprises of 4 DSP tiles, all of which perform part of the DSP function and have
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different routing bit configurations. Structually they are similar to logic tiles, but with the DSP
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function wired into where the LUTs and DFFs would be. The four types of DSP tiles will be referred to
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as DSP0 through DSP3, with DSP0 at the lowest y-position. One signal CO, is also routed through the
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IPConnect tile above the DSP tile, referred to as IPCON4 in this context.
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A work-in-progress effort to determine where signals and configuration bits are located is below:</p>
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<p>
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<strong>Signal Assignments</strong><br/>
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<table class="ctab">
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<tr><th>SB_MAC16 port</th><th>DSP0</th><th>DSP1</th><th>DSP2</th><th>DSP3</th><th>IPCON4</th></tr>
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<tr><td>CLK</td><td>-</td><td>-</td><td>lutff_global/clk</td><td>-</td><td>-</td></tr>
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<tr><td>CE</td><td>-</td><td>-</td><td>lutff_global/cen</td><td>-</td><td>-</td></tr>
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<tr><td>C[7:0]</td><td>-</td><td>-</td><td>-</td><td>lutff_[7:0]/in_3</td><td>-</td></tr>
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<tr><td>C[15:8]</td><td>-</td><td>-</td><td>-</td><td>lutff_[7:0]/in_1</td><td>-</td></tr>
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<tr><td>A[7:0]</td><td>-</td><td>-</td><td>lutff_[7:0]/in_3</td><td>-</td><td>-</td></tr>
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<tr><td>A[15:8]</td><td>-</td><td>-</td><td>lutff_[7:0]/in_1</td><td>-</td><td>-</td></tr>
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<tr><td>B[7:0]</td><td>-</td><td>lutff_[7:0]/in_3</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>B[15:8]</td><td>-</td><td>lutff_[7:0]/in_1</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>D[7:0]</td><td>lutff_[7:0]/in_3</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>D[15:8]</td><td>lutff_[7:0]/in_1</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>IRSTTOP</td><td>-</td><td>lutff_global/s_r</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>IRSTBOT</td><td>lutff_global/s_r</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>ORSTTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_global/s_r</td><td>-</td></tr>
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<tr><td>ORSTBOT</td><td>-</td><td>-</td><td>lutff_global/s_r</td><td>-</td><td>-</td></tr>
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<tr><td>AHOLD</td><td>-</td><td>-</td><td>lutff_0/in_0</td><td>-</td><td>-</td></tr>
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<tr><td>BHOLD</td><td>-</td><td>lutff_0/in_0</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>CHOLD</td><td>-</td><td>-</td><td>-</td><td>lutff_0/in_0</td><td>-</td></tr>
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<tr><td>DHOLD</td><td>lutff_0/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>OHOLDTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_1/in_0</td><td>-</td></tr>
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<tr><td>OHOLDBOT</td><td>lutff_1/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>ADDSUBTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_3/in_0</td><td>-</td></tr>
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<tr><td>ADDSUBBOT</td><td>lutff_3/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>OLOADTOP</td><td>-</td><td>-</td><td>-</td><td>lutff_2/in_0</td><td>-</td></tr>
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<tr><td>OLOADBOT</td><td>lutff_2/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>CI</td><td>lutff_4/in_0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
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<tr><td>O[31:0]</td><td>mult/O_[7:0]</td><td>mult/O_[15:8]</td><td>mult/O_[23:16]</td><td>mult/O_[31:24]</td><td>-</td></tr>
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<tr><td>CO</td><td>-</td><td>-</td><td>-</td><td>-</td><td>slf_op_0</td></tr>
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</table>
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</p>
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<p>
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<strong>Configuration Bits</strong><br/>
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<p>The DSP configuration bits mostly follow the order stated in the ICE Technology Library document, where they are described as<span style="font-family:monospace">CBIT[24:0]</span>. For most DSP tiles,
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these follow a logical order where <span style="font-family:monospace">CBIT[7:0]</span> maps to DSP0 <span style="font-family:monospace">CBIT[7:0]</span>; <span style="font-family:monospace">CBIT[15:8]</span>
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to DSP1 <span style="font-family:monospace">CBIT[7:0]</span>, <span style="font-family:monospace">CBIT[23:16]</span> to DSP2 <span style="font-family:monospace">CBIT[7:0]</span>
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and <span style="font-family:monospace">CBIT[24]</span> to DSP3 <span style="font-family:monospace">CBIT0</span>.
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</p>
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<p>However, there are some locations where configuration bits are swapped between DSP tiles and IPConnect tiles. For example, DSP1 (0, 16) <span style="font-family:monospace">CBIT[4:3]</span> is used
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for the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) <span style="font-family:monospace">CBIT[6:5]</span>.</p>
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<p>The exact permutations are not yet known, but a script will be developed to find them.</p>
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<p>
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<strong>Other Implementation Notes</strong><br/>
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<p>
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All active DSP tiles, and all IPConnect tiles whether used or not, have some bits set which reflect their logic tile heritage. The <span style="font-family:monospace">LC_<em>x</em></span>
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bits which would be used to configure the logic cell, are set to the below pattern for each "logic cell" (interpreting them like a logic tile):<br/>
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<br><span style="font-family:monospace">0000111100001111 0000</span><br/><br/>
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Coincidentally or not, this corresponds to a buffer passing through input 2 to the output. For each "cell" the cascade bit <span style="font-family:monospace">LC0<em>x</em>_inmux02_5</span> is
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also set, effectively creating one large chain, as this connects input 2 to the output of the previous LUT. It is not yet known if this serves any purpose, or is merely a remainder of Lattice's
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internal testing.
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</p>
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</p>
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<h2>IPConnect Tiles</h2>
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<p>IPConnect tiles are used for connections to all of the other UltraPlus features, such as I2C/SPI, SPRAM, RGB and oscillators. Like DSP tiles,
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they are structually similar to logic tiles. The outputs of IP functions are connected to nets named <span style="font-family:monospace">slf_op_0</span> through <span style="font-family:monospace">slf_op_7</span>,
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and the inputs use the LUT/FF inputs in the same way as DSP tiles.</p>
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<h2>Internal Oscillators</h2>
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Both of the internal oscillators are connected through IPConnect tiles, with their outputs optionally connected to the global networks,
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by setting the "padin" extra bit (the used global networks 4 and 5 don't have physical pins on UltraPlus devices).
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<h3>SB_HFOSC</h3>
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<p>The <span style="font-family:monospace">CLKHFPU</span> input connects through IPConnect tile (0, 29) input <span style="font-family:monospace">lutff_0/in_1</span>;
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and the <span style="font-family:monospace">CLKHFEN</span> input connects through input <span style="font-family:monospace">lutff_7/in_3</span> of the same tile.<br/>
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The <span style="font-family:monospace">CLKHF</span> output of SB_HFOSC is connected to both IPConnect tile (0, 28) output <span style="font-family:monospace">slf_op_7</span> and to the <span style="font-family:monospace">padin</span>
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of <span style="font-family:monospace">glb_netwk_4</span>.</p>
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<p>Configuration bit <span style="font-family:monospace">CLKHF_DIV[1]</span> maps to DSP1 tile (0, 16) config bit <span style="font-family:monospace">CBIT_4</span>, and
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<span style="font-family:monospace">CLKHF_DIV[0]</span> maps to DSP1 tile (0, 16) config bit <span style="font-family:monospace">CBIT_3</span>.</p>
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<h3>SB_LFOSC</h3>
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<p>The <span style="font-family:monospace">CLKLFPU</span> input connects through IPConnect tile (25, 29) input <span style="font-family:monospace">lutff_0/in_1</span>;
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and the <span style="font-family:monospace">CLKLFEN</span> input connects through input <span style="font-family:monospace">lutff_7/in_3</span> of the same tile.<br/>
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The <span style="font-family:monospace">CLKLF</span> output of SB_LFOSC is connected to both IPConnect tile (25, 29) output <span style="font-family:monospace">slf_op_0</span> and to the <span style="font-family:monospace">padin</span>
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of <span style="font-family:monospace">glb_netwk_5</span>.</p>
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<p>SB_LFOSC has no configuration bits.</p>
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</body></html>
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@ -956,7 +956,7 @@ def netname_normalize(netname, edge="", ramb=False, ramt=False, ramb_8k=False, r
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if ramb_8k: netname="ram/RADDR_%d" % ([7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, 10, 9, 8][idx1*4 + idx2])
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if ramt_8k: netname="ram/WADDR_%d" % ([7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, 10, 9, 8][idx1*4 + idx2])
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match = re.match(r"(...)_op_(.*)", netname)
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if match:
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if match and (match.group(1) != "slf"):
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netname = "neigh_op_%s_%s" % (match.group(1), match.group(2))
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if re.match(r"lutff_7/(cen|clk|s_r)", netname):
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netname = netname.replace("lutff_7/", "lutff_global/")
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@ -161,6 +161,7 @@ def is_interconn(netname):
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if netname.startswith("span12_"): return True
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if netname.startswith("logic_op_"): return True
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if netname.startswith("neigh_op_"): return True
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if netname.startswith("slf_op_"): return True
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if netname.startswith("local_"): return True
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return False
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@ -768,7 +769,7 @@ for i in range(4):
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#TEMP: for tracing only
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text_func.append("/* DSP%d %2d %2d */ assign dsp%d_%d_%d_clk = %s;" % (i, x, y, i, x, y, net_clk))
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text_func.append("/* DSP%d %2d %2d */ assign dsp%d_%d_%d_sr = %s;" % (i, x, y, i, x, y, net_sr))
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for j in range(7):
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for j in range(8):
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net_in0 = seg_to_net((x, y, "lutff_%d/in_0" % j), "1'b0")
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net_in1 = seg_to_net((x, y, "lutff_%d/in_1" % j), "1'b0")
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net_in2 = seg_to_net((x, y, "lutff_%d/in_2" % j), "1'b0")
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