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231 Commits

Author SHA1 Message Date
Matt Venn d06a967590 Update Claire's name and fix the reference image in the iceprog help 2025-06-03 11:06:08 +02:00
Miodrag Milanovic 1341137372 Generate chip database HTML 2025-02-07 12:43:20 +01:00
Miodrag Milanovic 68044cc4da Do not add wires for module ports 2025-01-20 15:37:01 +01:00
Miodrag Milanovic 7190770949 Resolve warning with python 3.12 2024-12-11 13:09:43 +01:00
Sylvain Munaut bb519401cd icebox: Add PLL ICEGATE function 
Only tested on UP5k. For others, it was just deduced.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2023-02-01 11:04:27 +01:00
gatecat e23274a9dd icebox: cb121 does have a PLL 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-25 15:52:44 +00:00
Miodrag Milanovic 9880f6e2dd Update variable name to PYTHON3 2021-09-06 11:11:52 +02:00
Miodrag Milanović f14a7fb4ca
Merge pull request #239 from xobs/python-bin-name 
Use $(PYTHON) in Makefiles instead of `python3`
 2021-09-06 11:08:23 +02:00
Miodrag Milanovic 9fe28369aa Fixes for macOS 2021-09-06 11:07:42 +02:00
Nils Albartus d969c333d0 added I2C and SPI for u4k to database 2020-12-04 16:47:05 +01:00
David Shah 4bc68c9620 Fix icebox_vlog for up5k 
Since ce1d811, SHIFTREG_DIV_MODE is now 2 bits for the up5k

Signed-off-by: David Shah <dave@ds0.me>
 2020-06-29 19:51:06 +01:00
Sylvain Munaut ce1d811d21 icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5k 
This allows selection of the div-by-5 mode of the PLL.
This bit can't be fuzzed because it's not supported by the lattice
tools at all ...

This only works for sure on the UP5k.

I tested HX8k and it didn't support it, so I'm only adding this on
the known working FPGA.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-06-03 10:45:31 +02:00
Miodrag Milanovic 5e9fc56e0a Make sure that scripts find files on final install 2020-04-14 18:14:32 +02:00
eine 7a7c085e9b icebox: fix missing DESTDIR for icebox_chipdb 2020-04-10 19:10:00 +02:00
Miodrag Milanovic fe3086a733 Support custom PROGRAM_PREFIX 2020-04-10 10:05:17 +02:00
Sean Cross 5280eae093 icebox: use $(PYTHON) variable in Makefile 
Allow `python` to be provided by an interpreter other than `python3`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-22 14:09:15 +08:00
Clifford Wolf 2ccae0d386 Only dump memory initialization in icebox_vlog if present in ASC file, fixes #228 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-08 17:07:52 +02:00
David Shah 1cec1328e0 up5k: Fix TOPADDSUB_CARRYSELECT_0 override where it swaps with osc trimming 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-03 12:54:00 +01:00
Simon Schubert 56978cde58 add RGB_DRV/LED_DRV_CUR for u4k 2019-06-10 13:06:11 +02:00
Michael Buesch eec6555603 icebox_vlog: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch 00213ed9c3 icebox_stat: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch 51a11ffc81 icebox_maps: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch e0642ba06e icebox_html: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch c9e741cfbc icebox_hlc2asc: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch 30769bbfd0 icebox_explain: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch 52bbe0f469 icebox_diff: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch c4ac25e096 icebox_colbuf: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch d26ac8d09e icebox_asc2hlc: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch 2aff52f10a icebox: Use cached re functions 2019-06-08 16:12:16 +02:00
Michael Buesch 795e0003f2 icebox: Add helper functions to LRU cache regular expression results 2019-06-08 16:12:16 +02:00
Michael Buesch 5f49bea71c icebox: Use LRU cache for often called function tile_has_net() 2019-06-08 16:12:07 +02:00
Simon Schubert be0bca0230 u4k: add SMCCLK cell location 
icecube uses SMCCLK.CLK to "legalize" output cells.  Unclear what this
is for, but it appears in almost all outputs.
 2019-02-22 22:35:55 +01:00
Simon Schubert d76ac32ec9 iCE40 Ultra = iCE5LP = u4k port 2019-02-22 22:35:55 +01:00
Clifford Wolf 5ab07ed32a
Merge pull request #178 from elmsfu/hlc/add_symbols_support 
hlc: parse '.sym>' to track signal names from HLC to ASC
 2018-10-10 13:46:31 +02:00
Andrew Wygle 9dbc14410f Add support for cm36 and swg25tr lm4k packages. 2018-08-28 08:29:53 -07:00
Keith Rothman 497028cf5a Add 5k support to hlc2asc. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2018-08-09 13:01:18 -07:00
Elms 542e9ef0f3 icebox: parse '.sym>' HLC to track signal names 2018-07-26 10:12:56 -07:00
Elms 61aa5c5094 icebox_hlc2asc: fix _lut_ keyword parsing 
'self.lut_bits is None' was always false. The _lut_ keyword is used by asc2hlc, so when converting asc->hlc->asc the lut_bits were always all zeros.
 2018-07-19 16:03:20 -07:00
Larry Doolittle e0eaaf5b91 Spelling fixes in messages 2018-07-19 13:59:42 +02:00
Tim 'mithro' Ansell 22f10b9e22 hlc: Use glb_network for current device. 
Previously the 1k global networks were hard coded. This now uses the
values from the given part.
 2018-07-16 18:05:49 -07:00
Clifford Wolf 763eb0f217
Merge pull request #168 from elmsfu/hlc2asc/verilog_literal_ram_data 
icebox_hlc2asc: Allow data of ram to use verilog literal format
 2018-07-10 21:21:13 +02:00
Clifford Wolf 9ccdd95ff7
Merge pull request #167 from mithro/icebox_vlog_drivers 
icebox_vlog: Better information about drivers for nets.
 2018-07-10 21:20:59 +02:00
Clifford Wolf 2d1f1f6258
Merge pull request #164 from mithro/global-fix 
Fix spelling and io_X/GLOBAL_OUTPUT_NETWORK
 2018-07-10 21:20:20 +02:00
Tim 'mithro' Ansell d0f654b0c6 icebox_vlog: Fix constant LUT output. 2018-07-08 18:18:56 -07:00
Tim 'mithro' Ansell ef618927ca icebox_vlog: Save error message to file and print it. 
Previously if you were doing;

`icebox_vlog example.asc > example_bit.v` you would just get;

```
Traceback (most recent call last):
  File "icebox_vlog.py", line 947, in <module>
    assert False
AssertionError
```

Now you get;
```
Traceback (most recent call last):
  File "icebox_vlog.py", line 948, in <module>
    assert False, "\n  ".join(emsg)
AssertionError: Single-driver-check failed for 2 nets:
  n10 has 0 drivers: []
  n15 has 2 drivers: ['clk', 'clk2']
```
 2018-07-08 15:59:53 -07:00
Elms 41ac3eaeab icebox_hlc2asc: Allow data of ram to use verilog literal format 2018-07-03 11:31:43 -07:00
Tim 'mithro' Ansell b2e1df618c icebox_vlog: Better information about drivers for nets. 2018-07-03 11:21:07 -07:00
Tim 'mithro' Ansell a3ae94cbeb icebox_hlc2asc: Allow io_X/GLOBAL_OUTPUT_BUFFER 2018-06-22 21:44:48 -07:00
Tim 'mithro' Ansell e2adc23681 icebox_hlc2asc: Fix spelling in error message. 2018-06-22 21:44:39 -07:00
Elms ac47e8e13c icebox_hlc2asc: update to support device by family 2018-06-20 07:31:19 -07:00