 Alan Mishchenko
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f329105403
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Adding barrier buffers.
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2014-03-18 12:51:39 -07:00 |
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Alan Mishchenko
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89eed1aaf9
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Adding barrier buffers.
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2014-03-16 21:56:28 -07:00 |
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Alan Mishchenko
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c97a9c0d18
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Changes to LUT mappers.
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2014-03-09 20:21:09 -07:00 |
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Alan Mishchenko
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737e4671ce
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Adding check for the presence of precomputed data.
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2013-12-29 14:39:25 +07:00 |
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Alan Mishchenko
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227963f03d
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New command &write_cnf.
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2013-12-18 00:22:26 +07:00 |
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Alan Mishchenko
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681483c904
|
Bug fixes in the above patches.
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2013-12-03 00:38:37 -08:00 |
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Alan Mishchenko
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34ab59574e
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Suggested patch of AIG writers.
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2013-12-03 00:26:43 -08:00 |
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Alan Mishchenko
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b21447b6df
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Bug fix in writing constants in write_verilog.
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2013-11-21 11:39:57 -08:00 |
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Alan Mishchenko
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cb4631e64e
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Compiler warnings.
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2013-10-17 18:04:07 -07:00 |
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|
Alan Mishchenko
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efa6b54b5e
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Debugging and finetuning the flow.
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2013-09-17 21:47:39 -07:00 |
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Alan Mishchenko
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7d3976a763
|
Unifying standard cell library representations.
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2013-09-17 13:16:20 -07:00 |
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Alan Mishchenko
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d1b9ade535
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Adding switch 'ps -s' to skip counting buffers/inverters as nodes.
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2013-09-02 23:15:15 -07:00 |
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Alan Mishchenko
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b6cb626a12
|
Removing some old useless code.
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2013-09-02 22:14:20 -07:00 |
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Alan Mishchenko
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e16e3edae8
|
Removing some old useless code.
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2013-09-02 22:10:27 -07:00 |
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Alan Mishchenko
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a206287b21
|
Adding support for input slew and output capacitance to timer and gate-sizer (bug fix).
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2013-07-24 11:42:37 -07:00 |
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Alan Mishchenko
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84c0b9d69b
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Tuning standard-cell mapping flow.
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2013-07-23 16:15:03 -07:00 |
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Alan Mishchenko
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a9afe7e8b7
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Improvements to post-mapping re-sizing.
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2013-07-21 14:56:30 -07:00 |
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|
Alan Mishchenko
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710835f8d6
|
Memory leaks.
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2013-07-21 01:28:54 -07:00 |
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Alan Mishchenko
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ab84c73eb0
|
Adding support for input slew (.input_drive) and output capacitance (.output_load) in BLIF reader/writer.
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2013-07-21 00:15:24 -07:00 |
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Alan Mishchenko
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19c25fd6aa
|
Adding a wrapper around clock() for more accurate time counting in ABC.
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2013-05-27 15:09:23 -07:00 |
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Alan Mishchenko
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d5234332fb
|
New MFS package.
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2013-05-24 22:35:22 -07:00 |
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Alan Mishchenko
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533ff6984e
|
Commenting assertion that does not hold in AIGER 1.9, accoring to Baruch Sterin.
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2013-05-13 23:25:34 -07:00 |
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Alan Mishchenko
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df198d2cef
|
Enabled 'cec' to be applied to networks derived from BLIF with EXDCs.
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2013-04-18 18:32:58 -07:00 |
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|
Alan Mishchenko
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c80fce00fe
|
Enabled reading the EXDC network by the default BLIF reader.
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2013-04-18 17:39:13 -07:00 |
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Alan Mishchenko
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96b784ecd7
|
Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except for liveness properties).
|
2013-04-18 00:05:11 -07:00 |
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Alan Mishchenko
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61ecc9c633
|
Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except for liveness properties).
|
2013-04-17 23:48:58 -07:00 |
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|
Alan Mishchenko
|
9b6efa34ad
|
Bug fix in 'write_pla'.
|
2013-04-15 22:59:54 -07:00 |
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|
Alan Mishchenko
|
4ff5203f4c
|
Improvements to the hierarchy/timing manager.
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2013-03-05 13:13:15 -08:00 |
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|
Alan Mishchenko
|
7e598cd231
|
Fixing compilation problems on Linux-32 related to constants of type unsigned long long.
|
2013-01-30 16:15:53 +07:00 |
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|
Alan Mishchenko
|
1b6662ce4a
|
Fixing C++ compilation issues.
|
2013-01-08 14:16:59 +08:00 |
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|
Alan Mishchenko
|
db7852bba7
|
Improvements to LMS code.
|
2012-11-06 18:04:23 -08:00 |
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|
Alan Mishchenko
|
fac3976621
|
Adding binary file dumping for truth tables.
|
2012-10-25 13:55:04 -07:00 |
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|
Alan Mishchenko
|
059da57476
|
Adding binary file dumping for truth tables.
|
2012-10-25 11:45:19 -07:00 |
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|
Alan Mishchenko
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7ecea8d40d
|
Added hierarchical BLIF output for mapping with LUT structures (write_blif -a -S <XYZ>).
|
2012-10-24 21:12:50 -07:00 |
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|
Alan Mishchenko
|
7235d74010
|
Bug fix in hierarchical BLIF reader.
|
2012-10-11 23:25:40 -07:00 |
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|
Alan Mishchenko
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d261e617fc
|
Added command to transform GIA into the file with truth tables for each output.
|
2012-10-10 01:11:24 -07:00 |
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Alan Mishchenko
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4ed89d00fe
|
Making explicit cast to 64-bit unsigned in a few places.
|
2012-10-09 09:23:08 -07:00 |
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|
Alan Mishchenko
|
56d3d7cd22
|
C++ portability changes.
|
2012-10-03 21:49:18 -07:00 |
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|
Alan Mishchenko
|
71bdfae941
|
Replacing 'st_table' by 'st__table' to resolve linker problems.
|
2012-09-29 17:11:03 -04:00 |
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|
Alan Mishchenko
|
aed3b3a13a
|
Cleaned up interfaces of genlib/liberty/supergate reading/writing.
|
2012-09-25 01:34:26 -07:00 |
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|
Alan Mishchenko
|
d0197d8378
|
Changed printouts in a few places in supergate computation.
|
2012-09-24 22:57:01 -07:00 |
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|
Alan Mishchenko
|
5f09917c22
|
Added simplification before the concurrent call to PDR.
|
2012-09-20 19:51:39 -07:00 |
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|
Alan Mishchenko
|
266af49386
|
Modified 'read' to read all types of libraries (genlib, liberty, scl).
|
2012-09-20 13:12:51 -07:00 |
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|
Alan Mishchenko
|
bc44087bac
|
Modified 'read' to read all types of libraries (genlib, liberty, scl).
|
2012-09-20 12:41:59 -07:00 |
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|
Alan Mishchenko
|
f59de3decc
|
Fixes to Verilog parser.
|
2012-09-20 11:29:37 -07:00 |
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|
Alan Mishchenko
|
5dc50744f0
|
Extending Liberty parser to handle multi-output cells.
|
2012-09-19 18:42:00 -07:00 |
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|
Alan Mishchenko
|
480ca14c75
|
Extending Liberty parser to handle multi-output cells.
|
2012-09-19 17:35:04 -07:00 |
|
|
Alan Mishchenko
|
3af0f719af
|
Extending BLIF parser/write to hangle multi-output cells.
|
2012-09-19 16:28:06 -07:00 |
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|
Alan Mishchenko
|
69bbfa9856
|
Created new abstraction package from the code that was all over the place.
|
2012-09-15 23:27:46 -07:00 |
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|
Alan Mishchenko
|
a246882a5b
|
Scalable gate-level abstraction.
|
2012-09-11 19:11:51 -07:00 |
|