mirror of https://github.com/YosysHQ/abc.git
Bug fix in writing constants in write_verilog.
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@ -523,7 +523,7 @@ void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk )
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{
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Mio_Gate_t * pGate = (Mio_Gate_t *)pObj->pData;
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Mio_Pin_t * pGatePin;
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if ( Abc_ObjFaninNum(pObj) == 0 )
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if ( Abc_ObjFaninNum(pObj) == 0 && (!strcmp(Mio_GateReadName(pGate), "_const0_") || !strcmp(Mio_GateReadName(pGate), "_const1_")) )
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{
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fprintf( pFile, " %-*s %s = 1\'b%d;\n", Length, "assign", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanout0(pObj) )), !strcmp(Mio_GateReadName(pGate), "_const1_") );
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continue;
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