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Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except for liveness properties).
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6
abc.rc
6
abc.rc
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@ -129,6 +129,12 @@ alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l;
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alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b"
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alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l"
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# use this script to convert 1-valued and DC-valued flops for an AIG
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alias fix_aig "logic; undc; strash; zero"
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# use this script to convert 1-valued and DC-valued flops for a logic network coming from BLIF
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alias fix_blif "undc; strash; zero"
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# lazy man's synthesis
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alias recadd3 "st; rec_add3; b; rec_add3; dc2; rec_add3; if -K 8; bidec; st; rec_add3; dc2; rec_add3; if -g -K 6; st; rec_add3"
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@ -780,6 +780,7 @@ Gia_Man_t * Gia_AigerReadFromMemory( char * pContents, int nFileSize, int fSkipS
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else
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{
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assert( Vec_IntEntry(vInits, i) == Abc_Var2Lit(Gia_ObjId(pNew, pObj), 0) );
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// unitialized value of the latch is the latch literal according to http://fmv.jku.at/hwmcc11/beyond1.pdf
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pInit[i] = 'X';
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}
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}
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@ -423,13 +423,19 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
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uLit0 = atoi( pCur ); while ( *pCur != ' ' && *pCur != '\n' ) pCur++;
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if ( *pCur == ' ' ) // read initial value
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{
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int Init;
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pCur++;
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if ( atoi( pCur ) == 0 )
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Init = atoi( pCur );
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if ( Init == 0 )
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Abc_LatchSetInit0( Abc_NtkBox(pNtkNew, i) );
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else if ( atoi( pCur ) == 1 )
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else if ( Init == 1 )
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Abc_LatchSetInit1( Abc_NtkBox(pNtkNew, i) );
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else
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{
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assert( Init == Abc_Var2Lit(1+Abc_NtkPiNum(pNtkNew)+i, 0) );
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// unitialized value of the latch is the latch literal according to http://fmv.jku.at/hwmcc11/beyond1.pdf
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Abc_LatchSetInitDc( Abc_NtkBox(pNtkNew, i) );
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}
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while ( *pCur != ' ' && *pCur != '\n' ) pCur++;
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}
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if ( *pCur != '\n' )
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