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64 Commits

Author SHA1 Message Date
Alan Mishchenko ecc27e80dc Adding support for the genlib library file name. 2025-03-10 14:37:29 -07:00
Alan Mishchenko 13998baf97 Allowing the genlib reader to skip gates larger than the given size. 2024-07-10 12:59:10 -07:00
Ethan Mahintorabi b7c7a6d98d
Fixes duplicate declaration of Abc_SclHasDelayInfo 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-02 02:15:59 +00:00
Alan Mishchenko 3e150dd553 Adding dumping of genlib library in Verilog. 2020-05-03 12:07:52 -07:00
Alan Mishchenko 396215532c Updates and bug fixes. 2017-10-04 12:37:38 +03:00
Alan Mishchenko c696ae95d0 Maintenance and updates. 2017-09-24 23:38:01 -07:00
Alan Mishchenko 3a1032c151 Maintenance and updates. 2017-09-18 08:27:05 -07:00
Alan Mishchenko d92bfbaddc Experiments with new network data-structure. 2017-03-20 23:45:03 -07:00
Alan Mishchenko c6afb9db63 Equivalent fault detection code. 2016-11-09 21:17:44 -08:00
Alan Mishchenko 7c089a3ac6 Factoring out library preprocessing code in &nf and putting it elsewhere. 2016-05-16 16:50:01 -07:00
Alan Mishchenko 20a2b0a0f2 Added switch 'read_genlib -n' to anonymize Genlib library. 2016-05-16 15:44:54 -07:00
Alan Mishchenko 22a5ab19c8 Adding API to convert Genlib into a simple Liberty. 2016-03-11 00:15:13 +09:00
Alan Mishchenko a4f9776388 Consolidating timing manager Scl_Con_t and propagating changes. 2016-01-07 16:50:01 -08:00
Alan Mishchenko c158dd5a94 Migrating to using 32-bit timing representation in &nf. 2016-01-05 16:40:00 -08:00
Alan Mishchenko 19ad75f125 Migrating back to using 'float' in area-flow computation in &nf. 2016-01-05 14:05:07 -08:00
Alan Mishchenko 19586f105c Adding code to support gate profiles. 2015-12-14 00:44:33 -08:00
Alan Mishchenko e9abb0f489 Adding code to support gate profiles. 2015-12-07 01:31:41 -08:00
Alan Mishchenko 0f29ba75f6 Adding commands to read/write/print gate profiles. 2015-12-05 18:10:43 -08:00
Alan Mishchenko 3c9f7d2bc8 Extending and improving timing manager. 2015-11-08 19:59:34 -08:00
Alan Mishchenko efb8ad0af8 Extending and improving timing manager. 2015-11-08 12:08:50 -08:00
Alan Mishchenko 35143e830b Experiments with precomputation and matching. 2015-10-27 10:48:40 -07:00
Alan Mishchenko 9519341aaf Extending library handling to 8 inputs. 2015-10-25 20:23:44 -07:00
Alan Mishchenko 61d4623207 Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only. 2015-10-23 17:17:23 -07:00
Alan Mishchenko 3712dd30d0 Changes for delay-oriented computation. 2015-10-23 15:14:31 -07:00
Alan Mishchenko 15a86aefd2 Experiments with precomputation and matching. 2015-10-15 15:32:36 -07:00
Alan Mishchenko 20c46b5a45 Experiments with precomputation and matching. 2015-10-12 18:29:15 -07:00
Alan Mishchenko faeeaeb5e7 Updating Mio to use int instead of float. 2015-08-31 15:09:46 -07:00
Alan Mishchenko 3de5d18c5f Adding APIs to retrieve NOR/OR gates from the library. 2015-04-14 18:53:28 +09:00
Alan Mishchenko b3e5ccd256 Getting default AND-node delay from Genlib library. 2015-04-06 10:56:14 +07:00
Alan Mishchenko 77dbe2b656 Major rehash of the CBA code. 2015-01-31 19:52:32 -08:00
Alan Mishchenko 7d81490fe6 Generating abstraction of standard cell library. 2014-07-25 20:02:56 -07:00
Alan Mishchenko 00efa68053 Several changes to allow Liberty files without delay info. 2013-11-21 12:58:13 -08:00
Alan Mishchenko 1692c1a57a Improvements to buffering and sizing. 2013-10-13 23:08:52 -07:00
Alan Mishchenko 7d3976a763 Unifying standard cell library representations. 2013-09-17 13:16:20 -07:00
Alan Mishchenko ff5d3591d1 Infrastructure to support full Liberty format and unitification of library representations. 2013-09-15 18:23:49 -07:00
Alan Mishchenko 4c6804c3ae Improved gate-sizing. 2013-07-29 10:10:21 -07:00
Alan Mishchenko 00d023713b Tuning standard-cell mapping flow. 2013-07-24 09:54:53 -07:00
Alan Mishchenko 4c00829900 Modified SCL gate library to read/write gate formula. 2013-03-26 20:19:50 -07:00
Alan Mishchenko 71bdfae941 Replacing 'st_table' by 'st__table' to resolve linker problems. 2012-09-29 17:11:03 -04:00
Alan Mishchenko e7527a47ba Cleaned up interfaces of genlib/liberty/supergate reading/writing. 2012-09-25 16:37:25 -07:00
Alan Mishchenko aed3b3a13a Cleaned up interfaces of genlib/liberty/supergate reading/writing. 2012-09-25 01:34:26 -07:00
Alan Mishchenko d0197d8378 Changed printouts in a few places in supergate computation. 2012-09-24 22:57:01 -07:00
Alan Mishchenko 5dc50744f0 Extending Liberty parser to handle multi-output cells. 2012-09-19 18:42:00 -07:00
Alan Mishchenko 3af0f719af Extending BLIF parser/write to hangle multi-output cells. 2012-09-19 16:28:06 -07:00
Alan Mishchenko 6d05fde2dc Added delay multipliers to 'map'. 2012-09-16 22:05:15 -07:00
Alan Mishchenko da6838463f Added features 'map -M <float>' to control the use of large gates. 2012-08-27 14:29:32 -07:00
Alan Mishchenko 8c1513dfbc Improving printouts of critical path. 2012-04-06 00:45:58 -07:00
Alan Mishchenko 0792ab0eb6 Additional features for delay optimization 2012-03-21 23:19:49 -07:00
Alan Mishchenko 8014f25f6d Major restructuring of the code. 2012-01-21 04:30:10 -08:00
Alan Mishchenko 1794bd37cd Made gate library package Mio independent of CUDD. 2011-03-30 21:02:29 -07:00