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5220 Commits

Author SHA1 Message Date
Allen Ho 6f5656c188 shared EI/EO not handled yet 2024-03-01 16:05:41 +08:00
Alan Mishchenko 1fd79c8430 Fixing a bug in input/output name ordering. 2024-02-29 15:19:47 -08:00
aletempiac fa8a277765 Changing search space exploration of ACD to search for better implementation and prune unnecessary computations based on theoretical properties 2024-02-29 17:16:49 +01:00
aletempiac 48b5f3b399 ACD66 performance improvements by avoiding unnecessary computation 2024-02-29 17:15:29 +01:00
aletempiac 75abcd376b Adding bindings to use ACD66 instead of generic ACD 2024-02-28 09:51:32 +01:00
aletempiac 44a65c23ed Adding relaxation on the maximum free set constraint 2024-02-27 17:47:43 +01:00
aletempiac d3f140f1df Performance improvements 2024-02-27 17:36:24 +01:00
aletempiac f72000f5ae Adding ACD cascade 666, performance improvements 2024-02-21 18:25:48 +01:00
aletempiac eba56b088f Cleaning code and performance improvements 2024-02-21 17:13:29 +01:00
aletempiac 13fd0d55c7 Removing unnecessary structs 2024-02-21 09:47:16 +01:00
aletempiac 0cd548f1cb Performance improvements to ACD 2024-02-20 17:28:50 +01:00
aletempiac 0e471e3ff8 Performance improvements of ACD 66 2024-02-20 14:41:52 +01:00
aletempiac 7b74810047 Changing policy of finding ACD 66 decomposition (faster and 100 percent coverage) 2024-02-16 16:43:24 +01:00
aletempiac 17afd93c78 Extending ACD to work up to 11 variables 2024-02-08 15:36:09 +01:00
aletempiac 3f80b202cd C++11 compatible code 2024-02-08 14:57:42 +01:00
aletempiac 2afaeac823 Adding hash table to reduce computations 2024-02-08 11:20:19 +01:00
aletempiac 2d9af6c9a4 Adding ACD for 66 LUT structure using a new method 2024-02-08 09:36:58 +01:00
Alan Mishchenko 52e0a10bf7 Fixing a compiler problem. 2024-02-05 20:49:36 -08:00
Alan Mishchenko e9a0bf6bf9 Adding reversing of simulation bits in &sim_read. 2024-02-05 20:32:11 -08:00
Alan Mishchenko d7ef3cc030 Bug fix in &fx. 2024-02-05 19:29:50 -08:00
Alan Mishchenko 62a22c7574 Bug fix in blasting multipliers with different argument bit-width. 2024-02-05 19:26:36 -08:00
Allen Ho c74144c6eb str_eco ver1 2024-02-01 07:25:46 +08:00
Alan Mishchenko 6d1d52deaa Adding an option to read the RTL elaboration library from the current directory. 2024-01-30 20:22:55 -08:00
Alan Mishchenko d6555f48dd Adding a switch to not write the timestamp in the AIGER file. 2024-01-26 07:31:20 -08:00
Alan Mishchenko 5fa9192412 Change how &stochsyn runs on a single core. 2024-01-18 18:34:50 -08:00
Alan Mishchenko 8da884de85 Switch to reverse the order of bits. 2024-01-18 18:23:11 -08:00
Baruch Sterin 234af64a8c Workaround for C++17 compilation (on clang) 2024-01-18 09:58:18 -08:00
Baruch Sterin d140535d64 Adapt previous merge by @aletempiac to compile with ABC namespaces. 2024-01-17 15:04:31 -08:00
aletempiac d223898f3d Merge remote-tracking branch 'origin/master' into acd 2024-01-16 17:44:45 +01:00
aletempiac 67aab70cff Moving ACD package to if folder 2024-01-16 17:42:43 +01:00
Alan Mishchenko 5bc99574fc Eliminating dependency on "abc.rc" in "&deepsyn". 2024-01-12 22:54:44 -08:00
aletempiac 38e632a954 Consider buffers in matrix covering as free 2024-01-12 14:50:34 +01:00
Alan Mishchenko 8c7327b8df Recognizing interface of the module when writing Verilog. 2024-01-11 22:19:50 -08:00
Alan Mishchenko dc68fe27f9 Saving module interface. 2024-01-11 19:45:42 -08:00
aletempiac 7dcc10a254 Minor fixes 2024-01-10 15:18:39 +01:00
alanminko 7f0a319564
Merge pull request #269 from rmlarsen/speedup_scanning 
Micro-optimizations to speed up the Liberty parser by ~1.67x.
 2023-12-21 12:58:42 +09:00
Alan Mishchenko 5978ccdb52 Updating sleep command to wait for file. 2023-12-21 12:16:33 +09:00
Rasmus Munk Larsen 706112ebd8 Micro-optimizations to speed up the Liberty parser by ~1.67x. 
Signed-off-by: Rasmus Munk Larsen <rmlarsen@google.com>
 2023-12-19 16:13:52 -08:00
Alan Mishchenko 7fe92148cc New command to put computation to sleep. 2023-12-18 21:04:31 +09:00
Allen Ho 284b9d6a9c extended box report; 2023-12-10 21:30:46 +08:00
Alan Mishchenko 16a3c5fc30 Add copying names in &saveaig and &loadaig. 2023-12-09 21:53:48 +08:00
Allen Ho 9bb5333f62 extend bo 2023-12-07 19:07:52 +08:00
aletempiac b3d2419d9a Formatting, renaming, and cleaning code 2023-11-27 13:38:36 +01:00
aletempiac 6097fd4349 Code formatting 2023-11-24 14:24:20 +01:00
aletempiac 23cfcc1e1f Improving efficiency and removing useless code 2023-11-24 12:18:49 +01:00
aletempiac 43f4dccb4f run time improvements in computing the column multiplicity 2023-11-23 16:29:33 +01:00
Allen Ho a316847341 correct fanout count 2023-11-23 19:33:05 +08:00
aletempiac acdd08fd9b Performance improvements 2023-11-21 11:47:56 +01:00
aletempiac d10d450f38 Final implementation 2023-11-19 21:59:40 +01:00
aletempiac 219d6d86d6 Simplifying code 2023-11-19 19:33:19 +01:00
aletempiac 672fd1b629 removing not used methods 2023-11-19 18:53:54 +01:00
aletempiac f7a520b957 restructuring code 2023-11-19 18:51:50 +01:00
aletempiac 1d7dfd25c6 Improving ACD mapping 2023-11-17 16:58:17 +01:00
aletempiac 3d602e2f00 Adding sorting of columns in heuristic covering 2023-11-17 15:55:10 +01:00
aletempiac 1ca7a3a353 Remove symmetries in covering table 2023-11-17 15:49:29 +01:00
aletempiac b77bdeeb17 Enabling ACD for area 2023-11-16 19:21:29 +01:00
aletempiac 8aa57c5d54 Decisions on late arrival 2023-11-16 18:53:02 +01:00
aletempiac 548fd6afb2 New version of enumeration of combinations 2023-11-16 18:20:05 +01:00
aletempiac b32bbdfef3 Improving set covering using unitary cost 2023-11-16 15:33:19 +01:00
aletempiac dcc960beba Adding local search for covering 2023-11-15 21:57:29 +01:00
aletempiac c07080f818 Adding heuristic set covering solver 2023-11-15 21:32:34 +01:00
aletempiac 66cdd36d20 Runtime improvements in decomposition 2023-11-15 19:03:29 +01:00
aletempiac 1632dc0d4e First version of ACD 2023-11-15 18:38:00 +01:00
Alan Mishchenko 6ca7eab466 Prototype of integrating decomposition into "if". 2023-11-14 12:58:03 -08:00
Alan Mishchenko eb264c5d22 Suggested fixes. 2023-11-13 17:19:54 -08:00
WWFUG 67a2b97cf0 added -I options in &bmiter 2023-11-08 19:00:03 +08:00
Alan Mishchenko 04dba9eed9 Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
Allen Ho 50010139ef why 2023-11-06 18:37:40 +08:00
Allen Ho ba64d6118b out-side box matching 2023-10-30 15:09:01 -07:00
Alan Mishchenko 5de12aa6b3 Experiments with SAT solving. 2023-10-23 11:30:44 -07:00
Alan Mishchenko 1bf21626c0 Bug fix. 2023-10-23 11:04:35 -07:00
Alan Mishchenko 76e8d21aaf Printout changes. 2023-10-23 10:48:43 -07:00
Alan Mishchenko 538ecb4515 Updating printouts. 2023-10-23 09:38:24 -07:00
Alan Mishchenko 01ad71b26f Experiments with verification. 2023-10-23 09:38:08 -07:00
Alan Mishchenko 8dbf8965fd Adding batch option to "scrgen". 2023-10-23 09:37:04 -07:00
Alan Mishchenko 652a0aaef7 Compiler warning. 2023-10-20 22:42:40 -07:00
Alan Mishchenko 72b423ba14 Experiments with SAT solving. 2023-10-20 20:53:43 -07:00
Alan Mishchenko 3c4c558656 Experiment with script generation. 2023-10-02 16:47:37 -07:00
Alan Mishchenko 65ccd3cc69 Enabled literal remapping. 2023-09-29 16:07:29 -07:00
Alan Mishchenko cc636a0d83 Experiments with verification. 2023-09-28 06:40:57 -07:00
Alan Mishchenko 0f11580fce Experiments with retiming. 2023-09-24 22:18:45 +08:00
Alan Mishchenko 4d1618f600 Enable dumping Verilog with assign-statements. 2023-09-21 11:08:43 +08:00
Alan Mishchenko 73dac01c15 Warning regarding PathMatchSpec() on Windows. 2023-09-21 11:08:16 +08:00
Allen Ho 31ad17fa1a add abc9RecoverBoundary 2023-09-20 14:23:47 +08:00
Alan Mishchenko 7fd4b01fb3 Automatic script file generation. 2023-09-18 16:30:09 +08:00
Alan Mishchenko 09b0295c1a Adding aliases for some commands. 2023-09-18 16:27:54 +08:00
Alan Mishchenko 9399faac48 Improvements to &gen_hie. 2023-09-17 12:40:33 +08:00
Alan Mishchenko 2f5b81119b Experiments with retiming. 2023-09-17 12:17:27 +08:00
Alan Mishchenko 475c8dad8e Compiler problem. 2023-09-16 07:13:10 +08:00
Cunxi Yu 1261f71248
Merge branch 'berkeley-abc:master' into master 2023-09-15 13:25:27 -07:00
Alan Mishchenko 318d5cb54b Do not create spec outputs in the boundary miter. 2023-09-15 23:10:42 +08:00
Alan Mishchenko 57cc2bd089 Compiler problem. 2023-09-15 22:51:11 +08:00
Alan Mishchenko 09013f3a6e New command &gen_hie to generate hierarchical designs. 2023-09-15 22:44:31 +08:00
wjrforcyber 3a53a950aa Refactor(Typo): Typo update on buffer 2023-09-12 11:57:18 +08:00
wjrforcyber 7fe7449685 Refactor(Typo):Typo update on dnsize 2023-09-12 10:40:59 +08:00
Alan Mishchenko 1153b3b6b9 Commenting out an assert that signals a non-critical formance bug. 2023-09-11 12:12:52 +07:00
Alan Mishchenko 1ffdbbbebe Corner-case bug fix. 2023-09-11 10:46:38 +07:00
Alan Mishchenko 588122dc72 Writing an interface module when dumping Verilog. 2023-09-11 09:44:22 +07:00
Alan Mishchenko 6d866dab6b Updating command "time" to report wall time. 2023-09-09 10:06:33 +07:00
Alan Mishchenko a4755a37cb Experiments with CEC. 2023-09-08 22:42:41 +07:00