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5873 Commits

Author SHA1 Message Date
Miodrag Milanovic e55d316cc9 WASI build fix 2025-04-08 17:38:54 +02:00
Miodrag Milanovic 20416c1a7b mingw fixes 2025-04-08 14:23:55 +02:00
Miodrag Milanovic 1cdaaadf53 Merge remote-tracking branch 'upstream/master' into yosys-experimental 2025-04-08 13:28:24 +02:00
Miodrag Milanovic 44a2996f7f Revert "Revert addition of CaDiCaL" 
This reverts commit 5ecc7c333c.
 2025-04-08 13:28:06 +02:00
alanminko 68c576cc56
Merge pull request #400 from MyskYko/rrr 
update rrr
 2025-04-07 11:34:13 +07:00
Alan Mishchenko 3846c193f2 Enable overlapping partitions in "stochmap". 2025-04-06 17:01:40 -07:00
MyskYko 27f2429d76 update rrr 2025-04-06 15:46:02 -07:00
Alan Mishchenko c0be439b45 Performance improvements. 2025-04-06 00:14:02 -07:00
Alan Mishchenko 1b6b553922 New commands for truth table file processing. 2025-04-05 22:40:24 -07:00
Alan Mishchenko 3f479dc84f Bug fixes in LUT cascade. 2025-04-05 22:39:59 -07:00
Alan Mishchenko 5c604949af Enable dumping of the resulting permutation of internal nodes in "permute". 2025-04-05 16:37:49 -07:00
Alan Mishchenko 96c28881a8 Bug fix in LUT cascade. 2025-04-01 19:03:17 -07:00
alanminko e3b96c784f
Merge pull request #396 from fxreichl/master 
Extend logging for eSLIM
 2025-04-01 20:35:49 +07:00
alanminko fa80e30eca
Merge pull request #386 from wjrforcyber/cmake_compilation_database 
Refactor(cmake): Generate compilation database
 2025-04-01 20:35:29 +07:00
alanminko a4d6775b7c
Merge pull request #384 from QiuYitai/master 
Fix the null reference vulnerability
 2025-04-01 20:35:09 +07:00
Franz Reichl 2c003f8865 Extend logging for eSLIM 2025-04-01 11:50:28 +02:00
Alan Mishchenko 29706ebede Bug with LUT cascade mapping. 2025-03-31 19:09:54 -07:00
Alan Mishchenko 80becaf2e2 Bug fix in LUT cascade decomposition. 2025-03-31 18:33:38 -07:00
Alan Mishchenko 9cdbb79338 Bug fix in handling concurrency in "stochmap". 2025-03-31 15:39:05 -07:00
Alan Mishchenko dc72d1e120 New command &store. 2025-03-31 15:24:15 -07:00
Alan Mishchenko 4656ae10e0 Updates to the GPC-based mapping. 2025-03-30 19:55:07 -07:00
Alan Mishchenko 6d6a5accb4 Experiments with LUT cascade mapping. 2025-03-30 18:20:55 -07:00
Alan Mishchenko 4ac014db41 Experiments with adder mapping. 2025-03-30 09:15:54 -07:00
Alan Mishchenko db2b52ca03 Bug fix. 2025-03-29 16:54:10 -07:00
Alan Mishchenko 2b5f102bdb Updating input file format in command "permute". 2025-03-29 15:48:07 -07:00
Alan Mishchenko bb11cc4c46 Experiments with adder-tree mapping. 2025-03-29 15:37:22 -07:00
Alan Mishchenko 2442720528 Adding counter generation to "symfun". 2025-03-29 11:11:13 -07:00
Alan Mishchenko 938ae9428b Extending interface of "permute". 2025-03-28 18:35:30 -07:00
Alan Mishchenko f5ac2d4bd3 Updates to LUT cascade decomposition. 2025-03-19 12:20:25 -07:00
Alan Mishchenko e320888191 Adding structural guidance. 2025-03-19 12:14:28 -07:00
alanminko da5f1e1579
Merge pull request #388 from fxreichl/master 
Circuit minimization with exact synthesis and SAT-based local improvement
 2025-03-19 19:50:37 +07:00
Franz Reichl 8ffca32372 Add command &eslim 2025-03-19 11:29:14 +01:00
Alan Mishchenko e7dd9151b1 Adding structural guidance. 2025-03-18 17:51:40 -07:00
Alan Mishchenko 2078b3945b Adding support for the random seed to the recent experiments. 2025-03-18 07:55:28 -07:00
Alan Mishchenko 30c952ed22 Remove structural choices after mapping. 2025-03-17 17:17:48 -07:00
Alan Mishchenko 59a7cc5c9c Removing intermediate files in exact synthesis. 2025-03-17 17:12:01 -07:00
Alan Mishchenko e20cbd6120 Updating command "cone" to extract a comma-separated list of outputs. 2025-03-17 16:10:22 -07:00
alanminko 80a43cce9e
Merge pull request #387 from chenjunhao0315/master 
stochmap heuristic adjust, rewire support level constraint and different mapper
 2025-03-17 10:09:15 +07:00
jiunhaochen e937e82cc6 rewire with &nf, &simap 2025-03-17 10:26:32 +08:00
jiunhaochen c63cf09660 rewire support level constraint 2025-03-17 10:26:32 +08:00
jiunhaochen 67d8095515 fix read_mm 2025-03-17 10:26:32 +08:00
jiunhaochen c3b76b1712 Patch rewire 2025-03-17 10:26:32 +08:00
Alan Mishchenko 0ebc9dbbae Experiments with exact synthesis. 2025-03-16 09:39:04 -07:00
Alan Mishchenko 839f3e18dd Experiments with mapping. 2025-03-14 20:24:08 -07:00
Alan Mishchenko aaba1b9a5f Experiments with mapping. 2025-03-13 20:59:17 -07:00
Alan Mishchenko d55735df2b Updates to the result reporting. 2025-03-13 11:57:53 -07:00
Alan Mishchenko 27fdbe0162 Updates to the mapping experiment. 2025-03-13 11:57:34 -07:00
Alan Mishchenko 2361a02c99 Fixing compilation problemj in some builds. 2025-03-12 20:53:02 -07:00
Alan Mishchenko feefa0f513 Supporting out of order signal names in AIGER reader. 2025-03-12 20:12:28 -07:00
Alan Mishchenko 5ef9c3c50b Experiment with mapping. 2025-03-12 20:11:33 -07:00