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Merge pull request #387 from chenjunhao0315/master 

stochmap heuristic adjust, rewire support level constraint and different mapper
This commit is contained in:
alanminko 2025-03-17 10:09:15 +07:00 committed by GitHub
parent 0ebc9dbbae e937e82cc6
commit 80a43cce9e
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GPG Key ID: B5690EEEBB952194
10 changed files with 247 additions and 122 deletions
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6
src/aig/gia/giaSatLut.c
View File

@ -1243,7 +1243,7 @@ Vec_Int_t * Gia_RunKadical( char * pFileNameIn, char * pFileNameOut, int nBTLimi
#ifdef _WIN32
char * pKadical = "kadical.exe";
#else
char * pKadical = "kadical";
char * pKadical = "./kadical";
#endif
char Command[1000], * pCommand = (char *)&Command;
if ( nBTLimit ) {
@ -1582,7 +1582,7 @@ int Gia_ManSimpleMapping( Gia_Man_t * p, int nBound, int nBTLimit, int nTimeout,
if ( fVerbose )
printf( "SAT variables = %d. SAT clauses = %d. Cardinality bound = %d. Conflict limit = %d. Timeout = %d.\n",
nVars, Vec_StrCountEntry(vStr, '\n'), nBound, nBTLimit, nTimeout );
Vec_Int_t * vRes = Gia_RunKadical( pFileNameI, pFileNameO, nBTLimit, nTimeout, 1, &Status );
Vec_Int_t * vRes = Gia_RunKadical( pFileNameI, pFileNameO, nBTLimit, nTimeout, fVerbose, &Status );
unlink( pFileNameI );
//unlink( pFileNameO );
if ( fKeepFile ) Gia_ManDumpCnf2( vStr, nVars, argc, argv, Abc_Clock() - clkStart, Status );
@ -1595,7 +1595,7 @@ int Gia_ManSimpleMapping( Gia_Man_t * p, int nBound, int nBTLimit, int nTimeout,
if ( fVerbose ) Gia_ManSimplePrintMapping( vRes, Gia_ManCiNum(p) );
p->vCellMapping = Gia_ManDeriveSimpleMapping( p, vRes );
Vec_IntFree( vRes );
Abc_PrintTime( 0, "Total time", Abc_Clock() - clkStart );
if ( fVerbose ) Abc_PrintTime( 0, "Total time", Abc_Clock() - clkStart );
return 1;
}

110
src/base/abci/abc.c
View File

@ -20427,15 +20427,15 @@ usage:
***********************************************************************/
int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
{
extern Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
extern Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
Abc_Ntk_t *pNtk, *pTemp;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nDist = 0;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nMappedMode = 0, nDist = 0;
float nLevelGrowRatio = 0;
Extra_UtilGetoptReset();
// Cmd_CommandExecute
pNtk = Abc_FrameReadNtk(pAbc);
while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMLVh" ) ) != EOF ) {
while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMALRVh" ) ) != EOF ) {
switch ( c ) {
case 'I':
if ( globalUtilOptind >= argc )
@ -20509,6 +20509,15 @@ int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
nMode = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'A':
if ( globalUtilOptind >= argc )
{
Abc_Print( -1, "Command line switch \"-M\" should be followed by a positive integer.\n" );
goto usage;
}
nMappedMode = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'L':
if ( globalUtilOptind >= argc )
{
@ -20518,6 +20527,15 @@ int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
nDist = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'R':
if ( globalUtilOptind >= argc )
{
Abc_Print( -1, "Command line switch \"-L\" should be followed by a positive number.\n" );
goto usage;
}
nLevelGrowRatio = atof(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'V':
if ( globalUtilOptind >= argc )
{
@ -20542,29 +20560,30 @@ int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -1, "Empty network.\n" );
return 1;
}
if ( nMode == 1 && Abc_FrameReadLibGen2() == NULL )
if ( nMode >= 1 && Abc_FrameReadLibGen2() == NULL )
{
Abc_Print( -1, "Library is not available.\n" );
return 1;
}
pTemp = Abc_ManRewire( pNtk, nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, nSeed, nVerbose );
pTemp = Abc_ManRewire( pNtk, nIters, nLevelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, nSeed, nVerbose );
Abc_FrameReplaceCurrentNetwork( pAbc, pTemp );
return 0;
usage:
Abc_Print( -2, "usage: rewire [-IEGDFSTV <num>]\n" );
Abc_Print( -2, "\t performs AIG re-wiring\n" );
Abc_Print( -2, "\t-I <num> : the number of iterations [default = %d]\n", nIters );
Abc_Print( -2, "\t-E <num> : the number of fanins to add to all nodes [default = %d]\n", nExpands );
Abc_Print( -2, "\t-G <num> : the number of fanins to add to one node [default = %d]\n", nGrowth );
Abc_Print( -2, "\t-D <num> : the number of shared divisors to extract [default = %d]\n", nDivs );
Abc_Print( -2, "\t-F <num> : the limit on the fanin count at a node [default = %d]\n", nFaninMax);
Abc_Print( -2, "\t-L <num> : localization distances [default = %d]\n", nDist);
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "transistor" : "node" );
Abc_Print( -2, "\t-S <num> : the random seed [default = %d]\n", nSeed );
Abc_Print( -2, "\t-T <num> : the timeout in seconds [default = unused]\n" );
Abc_Print( -2, "\t-V <num> : the verbosity level [default = %d]\n", nVerbose );
Abc_Print( -2, "usage: rewire [-IEGDFLRMASTV <num>]\n" );
Abc_Print( -2, "\t-I <num> : the number of iterations [default = %d]\n", nIters );
Abc_Print( -2, "\t-E <num> : the number of fanins to add to all nodes [default = %d]\n", nExpands );
Abc_Print( -2, "\t-G <num> : the number of fanins to add to one node [default = %d]\n", nGrowth );
Abc_Print( -2, "\t-D <num> : the number of shared divisors to extract (-1: unlimited) [default = %d]\n", nDivs );
Abc_Print( -2, "\t-F <num> : the limit on the fanin count at a node [default = %d]\n", nFaninMax);
Abc_Print( -2, "\t-L <num> : localization distances (0: unlimited) [default = %d]\n", nDist);
Abc_Print( -2, "\t-R <num> : level constraint (0: unlimited, 1: preserve level) [default = %g]\n", nLevelGrowRatio);
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "area" : "AIG node" );
Abc_Print( -2, "\t-A <num> : mapper (0: amap, 1: &nf, 2: &simap) (experimental) [default = %d]\n", nMappedMode );
Abc_Print( -2, "\t-S <num> : the random seed (0: random, >= 1: user defined) [default = %d]\n", nSeed );
Abc_Print( -2, "\t-T <num> : the timeout in seconds (0: unlimited) [default = %d]\n", nTimeOut );
Abc_Print( -2, "\t-V <num> : the verbosity level [default = %d]\n", nVerbose );
Abc_Print( -2, "\t-h : prints the command usage\n" );
Abc_Print( -2, "\n\tThis command was contributed by Jiun-Hao Chen from National Taiwan University.\n" );
return 1;
@ -45841,12 +45860,13 @@ usage:
***********************************************************************/
int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
{
extern Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
extern Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
Gia_Man_t *pTemp;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nDist = 0;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nMappedMode = 0, nDist = 0;
float nLevelGrowRatio = 0;
Extra_UtilGetoptReset();
// Cmd_CommandExecute
while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMLVh" ) ) != EOF ) {
while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMALRVh" ) ) != EOF ) {
switch ( c ) {
case 'I':
if ( globalUtilOptind >= argc )
@ -45920,6 +45940,15 @@ int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
nMode = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'A':
if ( globalUtilOptind >= argc )
{
Abc_Print( -1, "Command line switch \"-M\" should be followed by a positive integer.\n" );
goto usage;
}
nMappedMode = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'L':
if ( globalUtilOptind >= argc )
{
@ -45929,6 +45958,15 @@ int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
nDist = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'R':
if ( globalUtilOptind >= argc )
{
Abc_Print( -1, "Command line switch \"-L\" should be followed by a positive number.\n" );
goto usage;
}
nLevelGrowRatio = atof(argv[globalUtilOptind]);
globalUtilOptind++;
break;
case 'V':
if ( globalUtilOptind >= argc )
{
@ -45953,31 +45991,33 @@ int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -1, "Empty GIA network.\n" );
return 1;
}
if ( nMode == 1 && Abc_FrameReadLibGen2() == NULL )
if ( nMode >= 1 && Abc_FrameReadLibGen2() == NULL )
{
Abc_Print( -1, "Library is not available.\n" );
return 1;
}
pTemp = Gia_ManRewire( pAbc->pGia, nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, nSeed, nVerbose );
pTemp = Gia_ManRewire( pAbc->pGia, nIters, nLevelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, nSeed, nVerbose );
if ( pTemp->pName == NULL )
pTemp->pName = Abc_UtilStrsav(Extra_FileNameWithoutPath(pAbc->pGia->pName));
Abc_FrameUpdateGia( pAbc, pTemp );
return 0;
usage:
Abc_Print( -2, "usage: &rewire [-IEGDFSTV <num>]\n" );
Abc_Print( -2, "usage: &rewire [-IEGDFLRMASTV <num>]\n" );
Abc_Print( -2, "\t performs AIG re-wiring\n" );
Abc_Print( -2, "\t-I <num> : the number of iterations [default = %d]\n", nIters );
Abc_Print( -2, "\t-E <num> : the number of fanins to add to all nodes [default = %d]\n", nExpands );
Abc_Print( -2, "\t-G <num> : the number of fanins to add to one node [default = %d]\n", nGrowth );
Abc_Print( -2, "\t-D <num> : the number of shared divisors to extract [default = %d]\n", nDivs );
Abc_Print( -2, "\t-F <num> : the limit on the fanin count at a node [default = %d]\n", nFaninMax);
Abc_Print( -2, "\t-L <num> : localization distances [default = %d]\n", nDist);
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "transistor" : "node" );
Abc_Print( -2, "\t-S <num> : the random seed [default = %d]\n", nSeed );
Abc_Print( -2, "\t-T <num> : the timeout in seconds [default = unused]\n" );
Abc_Print( -2, "\t-V <num> : the verbosity level [default = %d]\n", nVerbose );
Abc_Print( -2, "\t-I <num> : the number of iterations [default = %d]\n", nIters );
Abc_Print( -2, "\t-E <num> : the number of fanins to add to all nodes [default = %d]\n", nExpands );
Abc_Print( -2, "\t-G <num> : the number of fanins to add to one node [default = %d]\n", nGrowth );
Abc_Print( -2, "\t-D <num> : the number of shared divisors to extract (-1: unlimited) [default = %d]\n", nDivs );
Abc_Print( -2, "\t-F <num> : the limit on the fanin count at a node [default = %d]\n", nFaninMax);
Abc_Print( -2, "\t-L <num> : localization distances (0: unlimited) [default = %d]\n", nDist);
Abc_Print( -2, "\t-R <num> : level constraint (0: unlimited, 1: preserve level) [default = %g]\n", nLevelGrowRatio);
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "area" : "AIG node" );
Abc_Print( -2, "\t-A <num> : mapper (0: amap, 1: &nf, 2: &simap) (experimental) [default = %d]\n", nMappedMode );
Abc_Print( -2, "\t-S <num> : the random seed (0: random, >= 1: user defined) [default = %d]\n", nSeed );
Abc_Print( -2, "\t-T <num> : the timeout in seconds (0: unlimited) [default = %d]\n", nTimeOut );
Abc_Print( -2, "\t-V <num> : the verbosity level [default = %d]\n", nVerbose );
Abc_Print( -2, "\t-h : prints the command usage\n" );
Abc_Print( -2, "\n\tThis command was contributed by Jiun-Hao Chen from National Taiwan University.\n" );
return 1;

6
src/base/abci/abcMap.c
View File

@ -930,15 +930,15 @@ Abc_Ntk_t * Abc_NtkFromMiniMapping( int *pArray )
// create pis
for ( i = 0; i < nCis-nFlops; i++ )
Abc_NtkCreatePi( pNtkMapped );
// create nodes
for ( i = 0; i < nNodes; i++ )
Abc_NtkCreateNode( pNtkMapped );
// create pos
for ( i = 0; i < nCos-nFlops; i++ )
Abc_NtkCreatePo( pNtkMapped );
// create flops
for ( i = 0; i < nFlops; i++ )
Abc_NtkAddLatch( pNtkMapped, NULL, ABC_INIT_ZERO );
// create nodes
for ( i = 0; i < nNodes; i++ )
Abc_NtkCreateNode( pNtkMapped );
// connect nodes
for ( i = 0; i < nNodes; i++ )
{

23
src/base/abci/abcPart.c
View File

@ -1612,6 +1612,7 @@ void Abc_NtkPermuteLevel( Abc_Ntk_t * pNtk, int Level )
Abc_ObjForEachFanout( pObj, pNext, k )
if ( Abc_ObjIsNode(pNext) )
LevelMax = Abc_MinInt( LevelMax, Abc_ObjLevel(pNext) );
if ( LevelMin == LevelMax ) continue;
assert( LevelMin < LevelMax );
// randomly set level between LevelMin and LevelMax-1
pObj->Level = LevelMin + (Abc_Random(0) % (LevelMax - LevelMin));
@ -1801,17 +1802,19 @@ Vec_Ptr_t * Abc_NtkDupWindows( Abc_Ntk_t * pNtk, Vec_Ptr_t * vvIns, Vec_Ptr_t *
}
Vec_Ptr_t * Abc_NtkExtractPartitions( Abc_Ntk_t * pNtk, int Iter, int nSuppMax, Vec_Ptr_t ** pvIns, Vec_Ptr_t ** pvOuts, Vec_Ptr_t ** pvNodes )
{
if ( Abc_NtkCiNum(pNtk) <= nSuppMax ) {
Vec_Ptr_t * vWins = Vec_PtrAlloc( 1 );
Vec_PtrPush( vWins, Abc_NtkDupDfs(pNtk) );
*pvIns = *pvOuts = *pvNodes = NULL;
return vWins;
}
int iUseRevL = Iter % 3 == 0 ? 0 : Abc_Random(0) & 1;
// if ( Abc_NtkCiNum(pNtk) <= nSuppMax ) {
// Vec_Ptr_t * vWins = Vec_PtrAlloc( 1 );
// Vec_PtrPush( vWins, Abc_NtkDupDfs(pNtk) );
// *pvIns = *pvOuts = *pvNodes = NULL;
// return vWins;
// }
// int iUseRevL = Iter % 3 == 0 ? 0 : Abc_Random(0) & 1;
int iUseRevL = Abc_Random(0) & 1;
int LevelMax = iUseRevL ? Abc_NtkLevelR(pNtk) : Abc_NtkLevel(pNtk);
int LevelCut = Iter % 3 == 0 ? 0 : LevelMax > 8 ? 2 + (Abc_Random(0) % (LevelMax - 4)) : 0;
//printf( "Using %s cut level %d (out of %d)\n", iUseRevL ? "reverse": "direct", LevelCut, LevelMax );
Abc_NtkPermuteLevel( pNtk, LevelMax );
// int LevelCut = Iter % 3 == 0 ? 0 : LevelMax > 8 ? 2 + (Abc_Random(0) % (LevelMax - 4)) : 0;
int LevelCut = LevelMax > 8 ? (Abc_Random(0) % (LevelMax - 4)) : 0;
// printf( "Using %s cut level %d (out of %d)\n", iUseRevL ? "reverse": "direct", LevelCut, LevelMax );
// Abc_NtkPermuteLevel( pNtk, LevelMax );
Vec_Wec_t * vStore = Vec_WecStart( LevelMax+1 );
Vec_Wec_t * vSupps = Abc_NtkCollectObjectsWithSuppLimit( pNtk, LevelCut, nSuppMax );
Vec_Ptr_t * vIns = Abc_NtkDeriveWinInsAll( vSupps, nSuppMax, pNtk );

29
src/opt/rar/rewire_map.c
View File

@ -29,24 +29,49 @@ extern Vec_Int_t * Abc_NtkWriteMiniMapping( Abc_Ntk_t * pNtk );
extern void Abc_NtkPrintMiniMapping( int * pArray );
extern Abc_Ntk_t * Abc_NtkFromMiniMapping( int *vMapping );
extern Mini_Aig_t * Abc_MiniAigFromNtk ( Abc_Ntk_t *pNtk );
extern void Nf_ManSetDefaultPars( Jf_Par_t * pPars );
extern Gia_Man_t * Nf_ManPerformMapping( Gia_Man_t * pGia, Jf_Par_t * pPars );
extern Abc_Ntk_t * Abc_NtkFromMappedGia( Gia_Man_t * p, int fFindEnables, int fUseBuffs );
extern Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p, int fUseBuffs );
extern int Gia_ManSimpleMapping( Gia_Man_t * p, int nBound, int nBTLimit, int nTimeout, int fVerbose, int fKeepFile, int argc, char ** argv );
Abc_Ntk_t *Gia_ManRewirePut(Gia_Man_t *pGia) {
Aig_Man_t *pMan = Gia_ManToAig(pGia, 0);
Abc_Ntk_t *pNtk = Abc_NtkFromAigPhase(pMan);
Abc_NtkSetName(pNtk, Abc_UtilStrsav(Gia_ManName(pGia)));
Aig_ManStop(pMan);
return pNtk;
}
Abc_Ntk_t *Abc_ManRewireMap(Abc_Ntk_t *pNtk) {
Abc_Ntk_t *Abc_ManRewireMapAmap(Abc_Ntk_t *pNtk) {
Amap_Par_t Pars, *pPars = &Pars;
Amap_ManSetDefaultParams(pPars);
Abc_Ntk_t *pNtkMapped = Abc_NtkDarAmap(pNtk, pPars);
if (pNtkMapped == NULL) {
Abc_NtkDelete(pNtk);
Abc_Print(-1, "Mapping has failed.\n");
return NULL;
}
return pNtkMapped;
}
Abc_Ntk_t *Gia_ManRewireMapNf(Gia_Man_t *pGia) {
Jf_Par_t Pars, * pPars = &Pars;
Nf_ManSetDefaultPars( pPars );
Gia_Man_t *pGiaNew = Nf_ManPerformMapping(pGia, pPars);
if (pGiaNew == NULL) {
Abc_Print(-1, "Mapping has failed.\n");
return NULL;
}
Abc_Ntk_t *pNtkMapped = Abc_NtkFromCellMappedGia(pGiaNew, 0);
return pNtkMapped;
}
Abc_Ntk_t *Gia_ManRewireMapSimap(Gia_Man_t *pGia, int nBound, int nBTLimit, int nTimeout) {
if (!Gia_ManSimpleMapping(pGia, nBound, nBTLimit, nTimeout, 0, 0, 0, NULL)) {
// Abc_Print(-1, "Mapping has failed.\n");
return NULL;
}
Abc_Ntk_t *pNtkMapped = Abc_NtkFromCellMappedGia(pGia, 0);
return pNtkMapped;
}

4
src/opt/rar/rewire_map.h
View File

@ -30,7 +30,9 @@
ABC_NAMESPACE_HEADER_START
Abc_Ntk_t *Gia_ManRewirePut(Gia_Man_t *pGia);
Abc_Ntk_t *Abc_ManRewireMap(Abc_Ntk_t *pNtk);
Abc_Ntk_t *Abc_ManRewireMapAmap(Abc_Ntk_t *pNtk);
Abc_Ntk_t *Gia_ManRewireMapNf(Gia_Man_t *pGia);
Abc_Ntk_t *Gia_ManRewireMapSimap(Gia_Man_t *pGia, int nBound, int nBTLimit, int nTimeout);
Vec_Int_t *Abc_ManRewireNtkWriteMiniMapping(Abc_Ntk_t *pNtk);
Abc_Ntk_t *Abc_ManRewireNtkFromMiniMapping(int *vMapping);
Mini_Aig_t *Abc_ManRewireMiniAigFromNtk(Abc_Ntk_t *pNtk);

145
src/opt/rar/rewire_miaig.cpp
View File

@ -26,29 +26,35 @@ ABC_NAMESPACE_IMPL_START
#endif // RW_ABC
#ifdef RW_ABC
Gia_Man_t *Gia_ManRewireInt(Gia_Man_t *pGia, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose) {
Random_Num(nSeed);
Gia_Man_t *Gia_ManRewireInt(Gia_Man_t *pGia, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose) {
Random_Num(nSeed == 0 ? Abc_Random(0) % 10 : nSeed);
Rewire::Miaig pNtkMiaig(pGia);
Rewire::Miaig pNew = pNtkMiaig.rewire(nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, fVerbose);
Rewire::Miaig pNew = pNtkMiaig.rewire(nIters, levelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, fVerbose);
pNew.setName(Gia_ManName(pGia));
return pNew.toGia();
}
Abc_Ntk_t *Abc_ManRewireInt(Abc_Ntk_t *pNtk, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose) {
Random_Num(nSeed);
Abc_Ntk_t *Abc_ManRewireInt(Abc_Ntk_t *pNtk, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose) {
Random_Num(nSeed == 0 ? Abc_Random(0) % 10 : nSeed);
int fMapped = nMode == 1;
Rewire::Miaig pNtkMiaig(pNtk);
Rewire::Miaig pNew = pNtkMiaig.rewire(nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, fVerbose);
Rewire::Miaig pNew = pNtkMiaig.rewire(nIters, levelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, fMapped, nMappedMode, nDist, fVerbose);
pNew.setName(Abc_NtkName(pNtk));
if (nMode == 2) {
pNew.countTransistors(1, nMappedMode);
}
return pNew.toNtk(nMode);
return pNew.toNtk(nMode >= 1);
}
Mini_Aig_t *MiniAig_ManRewireInt(Mini_Aig_t *pAig, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose) {
Random_Num(nSeed);
Mini_Aig_t *MiniAig_ManRewireInt(Mini_Aig_t *pAig, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose) {
Random_Num(nSeed == 0 ? Abc_Random(0) % 10 : nSeed);
Rewire::Miaig pNtkMiaig(pAig);
Rewire::Miaig pNew = pNtkMiaig.rewire(nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, fVerbose);
Rewire::Miaig pNew = pNtkMiaig.rewire(nIters, levelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, fVerbose);
return pNew.toMiniAig();
}
@ -84,6 +90,15 @@ void Miaig::create(int nIns, int nOuts, int nObjsAlloc) {
}
}
void Miaig::setName(char *pName) {
if (_data) {
if (_data->pName) {
free(_data->pName);
}
_data->pName = strdup(pName);
}
}
void Miaig::print(void) {
int i, k, iLit;
printf("\nAIG printout:\n");
@ -149,6 +164,7 @@ int Miaig::fromMiniAig(Mini_Aig_t *pMiniAig) {
Gia_Man_t *Miaig::toGia(void) {
int i, k, iLit, And2 = countAnd2();
Gia_Man_t *pGia = Gia_ManStart(1 + nIns() + And2 + nOuts()), *pTemp;
pGia->pName = Abc_UtilStrsav( _data->pName );
Gia_ManHashAlloc(pGia);
memset(_data->pCopy, 0, sizeof(int) * nObjs());
Miaig_ForEachInput(i)
@ -197,34 +213,63 @@ Mini_Aig_t *Miaig::toMiniAig(void) {
}
Abc_Ntk_t *Miaig::toNtk(int fMapped) {
Abc_Ntk_t *pNtk;
if (_data->pNtkMapped && fMapped) {
return Abc_ManRewireNtkFromMiniMapping(Vi_Array(_data->pNtkMapped));
pNtk = Abc_ManRewireNtkFromMiniMapping(Vi_Array(_data->pNtkMapped));
ABC_FREE(pNtk->pName);
Abc_NtkSetName(pNtk, Abc_UtilStrsav(_data->pName));
return pNtk;
}
Gia_Man_t *pGia = toGia();
Abc_Ntk_t *pNtk = Gia_ManRewirePut(pGia);
pNtk = Gia_ManRewirePut(pGia);
Gia_ManStop(pGia);
return pNtk;
}
vi *moveVecToVi(Vec_Int_t *v) {
vi *p = (vi *)malloc(sizeof(vi));
p->size = Vec_IntSize(v);
p->cap = Vec_IntCap(v);
p->ptr = Vec_IntArray(v);
free(v);
return p;
}
#endif // RW_ABC
// technology mapping
float Miaig::countTransistors(int reset) {
float Miaig::countTransistors(int reset, int nMappedMode) {
if (!reset && _data->nTransistor) return _data->nTransistor;
#ifdef RW_ABC
Abc_Ntk_t *pNtk = toNtk();
Abc_Ntk_t *pNtkMapped = Abc_ManRewireMap(pNtk);
float area = Abc_NtkGetMappedArea(pNtkMapped);
Vec_Int_t *vMapping = Abc_ManRewireNtkWriteMiniMapping(pNtkMapped);
_data->pNtkMapped = (vi *)malloc(sizeof(vi));
_data->pNtkMapped->size = Vec_IntSize(vMapping);
_data->pNtkMapped->cap = Vec_IntCap(vMapping);
_data->pNtkMapped->ptr = Vec_IntArray(vMapping);
free(vMapping);
Abc_NtkDelete(pNtk);
Abc_NtkDelete(pNtkMapped);
#else
float area = 0;
Abc_Ntk_t *pNtkMapped = NULL, *pNtkMappedTemp = NULL;
if (nMappedMode == 0) { // amap
Abc_Ntk_t *pNtk = toNtk();
pNtkMapped = Abc_ManRewireMapAmap(pNtk);
Abc_NtkDelete(pNtk);
} else if (nMappedMode == 1) { // &nf
Gia_Man_t *pGia = toGia();
pNtkMapped = Gia_ManRewireMapNf(pGia);
Gia_ManStop(pGia);
} else if (nMappedMode == 2) { // &simap
Abc_Ntk_t *pNtk = toNtk();
pNtkMapped = Abc_ManRewireMapAmap(pNtk);
area = Abc_NtkGetMappedArea(pNtkMapped);
Gia_Man_t *pGia = toGia();
while ((pNtkMappedTemp = Gia_ManRewireMapSimap(pGia, area - 2, 0, 40))) {
area -= 2;
Abc_NtkDelete(pNtkMapped);
pNtkMapped = pNtkMappedTemp;
}
Gia_ManStop(pGia);
}
if (pNtkMapped) {
area = Abc_NtkGetMappedArea(pNtkMapped);
Vec_Int_t *vMapping = Abc_ManRewireNtkWriteMiniMapping(pNtkMapped);
_data->pNtkMapped = moveVecToVi(vMapping);
Abc_NtkDelete(pNtkMapped);
}
#else
float area = countAnd2(reset, 0);
#endif // RW_ABC
return _data->nTransistor = area;
@ -892,7 +937,7 @@ int Miaig::checkConst(int iObj, word *pCare, int fVerbose) {
return 0;
}
int Miaig::expandOne(int iObj, int nAddedMax, int nDist, int fVerbose) {
int Miaig::expandOne(int iObj, int nAddedMax, int nDist, int nExpandableLevel, int fVerbose) {
int i, k, n, iLit, nAdded = 0;
word *pCare = computeCareSet(iObj);
assert(nAddedMax > 0);
@ -908,6 +953,7 @@ int Miaig::expandOne(int iObj, int nAddedMax, int nDist, int fVerbose) {
if (nDist) markDistanceN(iObj, nDist);
Miaig_ForEachInputNode(i) {
if (nDist && objDist(i) < 0 && !objIsPi(i)) continue;
// if (nExpandableLevel && objLevel(i) - objLevel(iObj) > nExpandableLevel) continue;
if (objTravId(i) != nTravIds() && (objIsPi(i) || (objFaninNum(i) > 1 && objRef(i) > 0))) // this node is NOT in the TFO
Vi_Push(_data->vOrderF, i);
}
@ -1010,8 +1056,8 @@ int Miaig::reduceOne(int iObj, int fOnlyConst, int fOnlyBuffer, int fHeuristic,
return 0;
}
int Miaig::expandThenReduceOne(int iNode, int nFaninAddLimit, int nDist, int fVerbose) {
expandOne(iNode, Abc_MinInt(Vi_Space(_data->pvFans + iNode), nFaninAddLimit), nDist, fVerbose);
int Miaig::expandThenReduceOne(int iNode, int nFaninAddLimit, int nDist, int nExpandableLevel, int fVerbose) {
expandOne(iNode, Abc_MinInt(Vi_Space(_data->pvFans + iNode), nFaninAddLimit), nDist, nExpandableLevel, fVerbose);
reduceOne(iNode, 0, 0, 0, fVerbose);
return 0;
}
@ -1025,7 +1071,7 @@ vi *Miaig::createRandomOrder(void) {
return _data->vOrder;
}
Miaig Miaig::expand(int nFaninAddLimitAll, int nDist, int fVerbose) {
Miaig Miaig::expand(int nFaninAddLimitAll, int nDist, int nExpandableLevel, int fVerbose) {
int i, iNode, nAdded = 0;
assert(nFaninAddLimitAll > 0);
vi *vOrder = createRandomOrder();
@ -1035,7 +1081,7 @@ Miaig Miaig::expand(int nFaninAddLimitAll, int nDist, int fVerbose) {
initializeLevels();
if (nDist) initializeDists();
Vi_ForEachEntry(vOrder, iNode, i) {
nAdded += expandOne(iNode, Abc_MinInt(Vi_Space(_data->pvFans + iNode), nFaninAddLimitAll - nAdded), nDist, fVerbose);
nAdded += expandOne(iNode, Abc_MinInt(Vi_Space(_data->pvFans + iNode), nFaninAddLimitAll - nAdded), nDist, nExpandableLevel, fVerbose);
if (nAdded >= nFaninAddLimitAll)
break;
}
@ -1071,7 +1117,7 @@ Miaig Miaig::reduce(int fVerbose) {
return dupStrash(1, 1, 1);
}
Miaig Miaig::expandThenReduce(int nFaninAddLimit, int nDist, int fVerbose) {
Miaig Miaig::expandThenReduce(int nFaninAddLimit, int nDist, int nExpandableLevel, int fVerbose) {
Miaig pTemp;
int i, iNode;
vi *vOrder = topoCollect();
@ -1081,15 +1127,15 @@ Miaig Miaig::expandThenReduce(int nFaninAddLimit, int nDist, int fVerbose) {
initializeLevels();
if (nDist) initializeDists();
Vi_ForEachEntry(vOrder, iNode, i) {
expandThenReduceOne(iNode, nFaninAddLimit, nDist, fVerbose);
expandThenReduceOne(iNode, nFaninAddLimit, nDist, nExpandableLevel, fVerbose);
}
verifyRefs();
return dupDfs().dupStrash(1, 1, 1);
}
Miaig Miaig::expandShareReduce(int nFaninAddLimitAll, int nDivs, int nDist, int nVerbose) {
Miaig Miaig::expandShareReduce(int nFaninAddLimitAll, int nDivs, int nDist, int nExpandableLevel, int nVerbose) {
// expand
Miaig pNew = expand(nFaninAddLimitAll, nDist, nVerbose);
Miaig pNew = expand(nFaninAddLimitAll, nDist, nExpandableLevel, nVerbose);
// share
pNew = pNew.share(nDivs == -1 ? pNew.nObjs() : nDivs);
// reduce
@ -1110,7 +1156,7 @@ Miaig randomRead(std::vector<Miaig> &pBests) {
return pBests[Random_Num(0) % pBests.size()];
}
Miaig Miaig::rewire(int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nVerbose) {
Miaig Miaig::rewire(int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nVerbose) {
const int nRootSave = 8;
const int nBestSave = 4;
int nRestart = 5000;
@ -1120,26 +1166,30 @@ Miaig Miaig::rewire(int nIters, int nExpands, int nGrowth, int nDivs, int nFanin
Miaig pNew;
Miaig pRoot = pRoots[0];
Miaig pBest = this->dup(0);
float (Miaig::*Miaig_ObjectiveFunction)(int) = (nMode == 0) ? &Miaig::countAnd2 : &Miaig::countTransistors;
float (Miaig::*Miaig_ObjectiveFunction)(int, int) = (nMode == 0) ? &Miaig::countAnd2 : &Miaig::countTransistors;
int maxLevel = levelGrowRatio != 0 ? this->countLevel() * levelGrowRatio : 0;
int nExpandableLevel = maxLevel ? maxLevel - this->countLevel() : 0;
float PrevBest = ((&pBest)->*Miaig_ObjectiveFunction)(1);
float PrevBest = ((&pBest)->*Miaig_ObjectiveFunction)(1, nMappedMode);
int iterNotImproveAfterRestart = 0;
if (nVerbose && maxLevel) printf("Max level : %5d\n", maxLevel);
if (nVerbose) printf("Initial target : %5g (AND2 = %5g Level = %3d)\n", PrevBest, this->countAnd2(1), this->countLevel());
for (int i = 0; i < nIters; i++) {
if (nVerbose) printf("\rIteration %7d : %5g -> ", i + 1, ((&pRoot)->*Miaig_ObjectiveFunction)(0));
for (int i = 0; nIters ? i < nIters : 1; i++) {
if (nVerbose) printf("\rIteration %7d : %5g -> ", i + 1, ((&pRoot)->*Miaig_ObjectiveFunction)(0, nMappedMode));
if (nTimeOut && nTimeOut < 1.0 * (Time_Clock() - clkStart) / CLOCKS_PER_SEC) break;
pNew = pRoot.dupMulti(nFaninMax, nGrowth);
if (i % 2 == 0) {
pNew = pNew.expandThenReduce(nGrowth, nDist, nVerbose > 1);
pNew = pNew.expandThenReduce(nGrowth, nDist, nExpandableLevel, nVerbose > 1);
}
pNew = pNew.expandShareReduce(nExpands, nDivs, nDist, nVerbose > 1);
pNew = pNew.expandShareReduce(nExpands, nDivs, nDist, nExpandableLevel, nVerbose > 1);
++iterNotImproveAfterRestart;
// report
float rootTarget = ((&pRoot)->*Miaig_ObjectiveFunction)(0);
float newTarget = ((&pNew)->*Miaig_ObjectiveFunction)(1);
if (PrevBest > newTarget) {
float rootTarget = ((&pRoot)->*Miaig_ObjectiveFunction)(0, nMappedMode);
float newTarget = ((&pNew)->*Miaig_ObjectiveFunction)(1, nMappedMode);
if (maxLevel ? pNew.countLevel() > maxLevel : 0) {
} else if (PrevBest > newTarget) {
if (nVerbose) printf("%5g (AND2 = %5g Level = %3d) ", newTarget, pNew.countAnd2(), pNew.countLevel());
if (nVerbose) Time_PrintEndl("Elapsed time", Time_Clock() - clkStart);
PrevBest = newTarget;
@ -1150,10 +1200,11 @@ Miaig Miaig::rewire(int nIters, int nExpands, int nGrowth, int nDivs, int nFanin
randomAddBest(pBests, pNew.dup(0), nBestSave);
}
// compare
if (rootTarget < newTarget) {
if (maxLevel ? pNew.countLevel() > maxLevel : 0) {
} else if (rootTarget < newTarget) {
if (iterNotImproveAfterRestart > nRestart) {
pNew = randomRead(pBests).dupMulti(nFaninMax, nGrowth);
pNew = pNew.expand(nExpands, nDist, nVerbose > 1);
pNew = pNew.expand(nExpands, nDist, nExpandableLevel, nVerbose > 1);
pNew = pNew.share(nDivs == -1 ? pNew.nObjs() : nDivs);
pNew = pNew.dupStrash(1, 1, 0);
pRoots = {pNew};

22
src/opt/rar/rewire_miaig.h
View File

@ -141,6 +141,7 @@ static inline int Rw_Lit2LitL(int *pMapV2L, int Lit) {
}
struct Miaig_Data {
char *pName; // network name
int refcount; // Reference counter
int nIns; // primary inputs
int nOuts; // primary outputs
@ -217,6 +218,7 @@ public:
void refObj(int iObj);
void derefObj(int iObj);
void derefObj_rec(int iObj, int iLitSkip);
void setName(char *pName);
private:
int initializeLevels_rec(int iObj);
@ -255,8 +257,9 @@ private:
int *hashLookup(int *pTable, int l0, int l1, int TableSize);
public:
float countAnd2(int reset = 0);
float countTransistors(int reset = 0);
float countAnd2(int reset = 0, int fDummy = 0);
// 0: amap 1: &nf 2: &simap
float countTransistors(int reset = 0, int nMode = 0);
int countLevel(void);
private:
@ -269,21 +272,21 @@ private:
int buildNodeCascade(Miaig &pNew, vi *vFanins, int fCprop, int fStrash);
private:
int expandOne(int iObj, int nAddedMax, int nDist, int fVerbose);
int expandOne(int iObj, int nAddedMax, int nDist, int nExpandableLevel, int fVerbose);
int reduceOne(int iObj, int fOnlyConst, int fOnlyBuffer, int fHeuristic, int fVerbose);
int expandThenReduceOne(int iNode, int nFaninAddLimit, int nDist, int fVerbose);
int expandThenReduceOne(int iNode, int nFaninAddLimit, int nDist, int nExpandableLevel, int fVerbose);
public:
Miaig dup(int fRemDangle, int fMapped = 0);
Miaig dupDfs(void);
Miaig dupStrash(int fCprop, int fStrash, int fCascade);
Miaig dupMulti(int nFaninMax_, int nGrowth);
Miaig expand(int nFaninAddLimitAll, int nDist, int nVerbose);
Miaig expand(int nFaninAddLimitAll, int nDist, int nExpandableLevel, int nVerbose);
Miaig share(int nNewNodesMax);
Miaig reduce(int fVerbose);
Miaig expandThenReduce(int nFaninAddLimit, int nDist, int fVerbose);
Miaig expandShareReduce(int nFaninAddLimitAll, int nDivs, int nDist, int nVerbose);
Miaig rewire(int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nVerbose);
Miaig expandThenReduce(int nFaninAddLimit, int nDist, int nExpandableLevel, int fVerbose);
Miaig expandShareReduce(int nFaninAddLimitAll, int nDivs, int nDist, int nExpandableLevel, int nVerbose);
Miaig rewire(int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nVerbose);
#ifdef RW_ABC
Gia_Man_t *toGia(void);
Abc_Ntk_t *toNtk(int fMapped = 0);
@ -355,6 +358,7 @@ inline void Miaig::addref(void) {
inline void Miaig::release(void) {
if (_refcount && RW_XADD(_refcount, -1) == 1) {
if (_data) {
if (_data->pName) free(_data->pName);
for (int i = 0; i < _data->nObjsAlloc; ++i)
if (_data->pvFans[i].ptr)
free(_data->pvFans[i].ptr);
@ -459,7 +463,7 @@ inline int Miaig::nWords(void) {
return _data->nWords;
}
inline float Miaig::countAnd2(int reset) {
inline float Miaig::countAnd2(int reset, int fDummy) {
int i, Counter = 0;
Miaig_ForEachNode(i) {
Counter += objFaninNum(i) - 1;

12
src/opt/rar/rewire_rar.c
View File

@ -22,16 +22,16 @@
ABC_NAMESPACE_IMPL_START
Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose) {
return Gia_ManRewireInt(pGia, nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, nSeed, fVerbose);
Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose) {
return Gia_ManRewireInt(pGia, nIters, levelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, nSeed, fVerbose);
}
Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose) {
return Abc_ManRewireInt(pNtk, nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, nSeed, fVerbose);
Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose) {
return Abc_ManRewireInt(pNtk, nIters, levelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, nSeed, fVerbose);
}
Mini_Aig_t *MiniAig_ManRewire(Mini_Aig_t *pAig, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose) {
return MiniAig_ManRewireInt(pAig, nIters, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nDist, nSeed, fVerbose);
Mini_Aig_t *MiniAig_ManRewire(Mini_Aig_t *pAig, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose) {
return MiniAig_ManRewireInt(pAig, nIters, levelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, nSeed, fVerbose);
}
ABC_NAMESPACE_IMPL_END

12
src/opt/rar/rewire_rar.h
View File

@ -35,12 +35,12 @@
ABC_NAMESPACE_HEADER_START
Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
Gia_Man_t *Gia_ManRewireInt(Gia_Man_t *pGia, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
Abc_Ntk_t *Abc_ManRewireInt(Abc_Ntk_t *pNtk, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
Mini_Aig_t *MiniAig_ManRewire(Mini_Aig_t *pAig, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
Mini_Aig_t *MiniAig_ManRewireInt(Mini_Aig_t *pAig, int nIters, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nDist, int nSeed, int fVerbose);
Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
Gia_Man_t *Gia_ManRewireInt(Gia_Man_t *pGia, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
Abc_Ntk_t *Abc_ManRewireInt(Abc_Ntk_t *pNtk, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
Mini_Aig_t *MiniAig_ManRewire(Mini_Aig_t *pAig, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
Mini_Aig_t *MiniAig_ManRewireInt(Mini_Aig_t *pAig, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fVerbose);
ABC_NAMESPACE_HEADER_END