luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,007 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

761 Commits

Author SHA1 Message Date
alanminko 547de09670
Merge pull request #145 from QuantamHD/fix_internal_pins 
Fixes internal pin parsing error in ASAP7 liberty file.
 2022-04-04 12:55:49 -07:00
Alan Mishchenko a24b15d03a Suggested changes for the case when the file begings with a new line. 2022-03-29 15:31:13 -07:00
Alan Mishchenko 5b8fa41ba9 Suggested bug fixes in the old code. 2022-01-21 11:33:53 -08:00
QuantamHD f288c4d7f6 Fixes internal pin parsing error in ASAP7 liberty file. 
This fix addresses an issue I saw with the ASAP7 liberty files and
ABC. ASAP7 lists internal pins in its liberty file which ABC's liberty
parser doesn't account for. This causes an assert to be triggered. This
fix simply adds interal pins to the ignore list.
 2021-12-20 12:55:11 -08:00
Alan Mishchenko ba64e78608 Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers. 2021-09-26 11:30:54 -07:00
Alan Mishchenko 787dbb9433 Two rare corner-case bugs in &if mapper. 2021-09-26 11:05:48 -07:00
Alan Mishchenko 9fac6c7a8b Experiments with CEC. 2021-07-10 10:50:33 -07:00
Alan Mishchenko 96b9192c78 Experiments with MUX decomposition. 2021-07-08 21:54:07 -07:00
Alan Mishchenko 8889ccb18c Updating LUT synthesis code. 2021-05-26 23:25:08 -07:00
Alan Mishchenko 9b75906740 Several changes for standard mapping. 2021-04-28 00:11:02 -07:00
Alan Mishchenko e463930709 Updating the mapper when user-specific matching is used. 2021-01-09 18:39:37 -08:00
Alan Mishchenko 73f8b598ac Rare bug fix in mapping with choices. 2020-10-29 17:21:37 -07:00
Alan Mishchenko e149cdcd77 Compiler warnings. 2020-05-03 12:15:54 -07:00
Alan Mishchenko 2b58a83ac0 Adding dumping of genlib library in Verilog. 2020-05-03 12:11:48 -07:00
Alan Mishchenko 559f8f5b5e Adding dumping of genlib library in Verilog. 2020-05-03 12:09:55 -07:00
Alan Mishchenko 3e150dd553 Adding dumping of genlib library in Verilog. 2020-05-03 12:07:52 -07:00
Alan Mishchenko dccd399255 Adding dynamic memory alloc for the buffer in Liberty file reader. 2020-01-11 07:12:48 +02:00
Alan Mishchenko f6dc4a588c Making sure arrival time of constant node is -infinity. 2020-01-02 17:58:05 -05:00
Alan Mishchenko feb3e7943d Adding limit on the depth of recursion when counting exact area in 'amap'. 2019-10-26 16:29:05 +03:00
Alan Mishchenko 3b4e9573bc Small bug in the unused code. 2019-10-04 10:47:46 -07:00
Alan Mishchenko b292595062 Adding switch to &if to consider special type of 6-input cuts. 2019-09-26 14:05:16 -07:00
Alan Mishchenko 390adc39ca Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to print delay profile. 2019-09-19 16:49:36 -07:00
Alan Mishchenko ee1bd8f0be Fixing some update gcc. 2019-07-24 11:44:28 +07:00
Alan Mishchenko 62487de97b Adding support for user-specified wire delays in &if. 2019-05-29 14:46:25 -07:00
Alan Mishchenko f0efc6e098 Prevent assertions from firing for deep logic networks. 2019-03-20 22:07:27 +02:00
Alan Mishchenko 01569b8f5f Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy, etc. 2019-03-05 15:57:50 -08:00
Alan Mishchenko b632c8496c Fixing some warnings with -Wconversion. 2019-03-05 15:07:10 -08:00
Alan Mishchenko 1f016988b2 Fixing float overflow during edge-flow computation in 'if' mapper (change to avoid dependence on the order of additions). 2018-12-12 22:15:10 -08:00
Alan Mishchenko 2f88284d7b Fixing float overflow during edge-flow computation in 'if' mapper. 2018-12-12 10:47:53 -08:00
Alan Mishchenko 5aa3025ce7 Adding switch &w -n to modify the comment section of the AIGER file written. 2018-11-21 13:12:01 -08:00
Alan Mishchenko 18943f6462 Skip cells in Liberty files which have dont_use attribute. 2018-10-18 17:09:23 +07:00
Alan Mishchenko d05fe039e1 Suggested bug fix in 'amap'. 2018-09-13 11:47:38 +03:00
Alan Mishchenko 7e9f3f027b Adding parameters and improvements to %blast. 2018-02-28 18:45:44 -08:00
Alan Mishchenko 76b00a2d3e Compilation problem with pow(). 2018-02-19 09:07:44 -08:00
Staf Verhaegen e4875df4e5 Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:54:38 +00:00
Alan Mishchenko accf4825e5 Adding API to dump MiniAIG into a Verilog file and other small changes. 2017-10-22 15:44:13 -07:00
Alan Mishchenko 1e1d41f3b8 Fix typo on the message reporting max output load. 2017-10-11 18:14:03 +07:00
Alan Mishchenko 396215532c Updates and bug fixes. 2017-10-04 12:37:38 +03:00
Alan Mishchenko c696ae95d0 Maintenance and updates. 2017-09-24 23:38:01 -07:00
Alan Mishchenko 287f9efcce Maintenance and updates. 2017-09-20 19:27:46 -07:00
Alan Mishchenko 3a1032c151 Maintenance and updates. 2017-09-18 08:27:05 -07:00
Alan Mishchenko 2e56f44c66 Compiler warnings. 2017-07-22 11:41:17 +07:00
Alan Mishchenko 859e769f22 Synchronizing various data-structures. 2017-07-04 15:23:51 -07:00
Alan Mishchenko bf6a053c64 Saturating floating point computation. 2017-07-01 13:48:31 -07:00
Alan Mishchenko a1dd7e3fb0 Saturating floating point computation. 2017-06-29 17:58:43 -07:00
Alan Mishchenko d92bfbaddc Experiments with new network data-structure. 2017-03-20 23:45:03 -07:00
Alan Mishchenko 19ccaf21df Experiments with new network data-structure. 2017-03-19 21:51:03 -07:00
Heinz Riener a20002dab1 stringizing macro argument 2017-03-03 12:03:55 +01:00
Alan Mishchenko 7d5b1c572b Restoring constraint manager to read old constraint file by default (use 'read_constr -n' to read new format). 2017-02-25 13:34:54 -08:00
Alan Mishchenko afcbb09717 Corner-case bug-fix in library preprocessor for standard-cell mapping. 2017-02-05 10:43:07 -08:00