 Alan Mishchenko
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47dde4e478
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Correcting incorrect handling of timing in several &-commands.
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2014-08-25 16:55:39 -07:00 |
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Alan Mishchenko
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cbbf78e6f4
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Improving print-out of 'dsd -p'.
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2014-08-22 22:18:38 -07:00 |
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Alan Mishchenko
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c344f3e38c
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Propagating timing support to the new synthesis/mapping commands.
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2014-08-20 22:12:51 -07:00 |
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Alan Mishchenko
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6dbaa4d0f8
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Extended command &cone to extract timing critical cones.
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2014-08-19 23:30:17 -07:00 |
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Alan Mishchenko
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3ef00645b8
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Added command 'sparsify' to derive ISF from CSF.
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2014-08-18 22:42:48 -07:00 |
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Alan Mishchenko
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65f9b73505
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Changing default CNF generation in &bmc.
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2014-08-18 20:19:32 -07:00 |
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Alan Mishchenko
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7c8136c82d
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Added DSD-based collapsing &dsd.
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2014-08-16 18:38:34 -07:00 |
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Alan Mishchenko
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97e620a4b7
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Adding specialized matching to 'if'.
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2014-08-16 18:28:41 -07:00 |
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Alan Mishchenko
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06100279cd
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Added DSD-based collapsing &dsd.
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2014-08-16 11:54:49 -07:00 |
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Alan Mishchenko
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f907347484
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Enabling circuit solver in &fraig.
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2014-08-12 18:54:43 -07:00 |
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Alan Mishchenko
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9055265394
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Bug fix in &fraig -L <num>.
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2014-08-12 16:23:52 -07:00 |
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Alan Mishchenko
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99a917caf3
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Bug fix in &fraig -L <num>.
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2014-08-12 16:20:03 -07:00 |
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Alan Mishchenko
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68ce0bc1c1
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Adding delay optimization to synthesis script &syn2.
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2014-08-08 12:45:28 -07:00 |
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Alan Mishchenko
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35b816dd57
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Enabling cofactoring in the mapper.
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2014-08-06 14:18:20 -07:00 |
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Alan Mishchenko
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1d9d6814ee
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Enabling ISOP-based minimization in 'collapse' if EXDC is available.
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2014-08-04 10:53:08 -07:00 |
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Alan Mishchenko
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edba505d9d
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Profiling code for SOP/DSD/LMS balancing.
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2014-08-02 17:01:48 -07:00 |
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Alan Mishchenko
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62bc45d1fb
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Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, such as [7:7], which seems to help in some cases.
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2014-08-02 17:00:24 -07:00 |
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Alan Mishchenko
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7fb1954268
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Small changes.
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2014-07-29 22:49:10 -07:00 |
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Alan Mishchenko
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6a69a9139c
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Adding support for standard-cell mapping.
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2014-07-28 11:31:31 -07:00 |
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Alan Mishchenko
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704b4bad6b
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Generating abstraction of standard cell library.
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2014-07-26 16:46:45 -07:00 |
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Alan Mishchenko
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7d81490fe6
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Generating abstraction of standard cell library.
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2014-07-25 20:02:56 -07:00 |
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Alan Mishchenko
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2cdc5ab850
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Bug fix in 'print_gates' due to the mix-up of the inverter.
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2014-07-22 17:23:48 -07:00 |
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Alan Mishchenko
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ba29267563
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Small changes.
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2014-07-21 22:43:08 -07:00 |
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Alan Mishchenko
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c0aa9b6a5d
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Adding new command &sopb for resource-aware SOP balancing.
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2014-07-21 13:49:25 -07:00 |
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Alan Mishchenko
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ea73401db5
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Updates and changes to several packages.
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2014-07-20 22:11:00 -07:00 |
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Alan Mishchenko
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4a861d868c
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Small changes in several packages.
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2014-07-17 09:47:07 -07:00 |
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Alan Mishchenko
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c58b57e2b4
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Improvements to profiling and printing statistics.
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2014-07-09 20:22:51 -07:00 |
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Alan Mishchenko
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b389f2054b
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Improvements to false path detection.
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2014-07-08 23:51:20 -07:00 |
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Alan Mishchenko
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afcec52a49
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Improvements to representation of choices.
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2014-07-01 13:05:09 -07:00 |
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Alan Mishchenko
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6bc381baa3
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Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_Ntk_t representing an AIG, by skipping object ID number 0 reserved for the constant node.
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2014-06-30 15:28:53 -07:00 |
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Alan Mishchenko
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1586d96c3e
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Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_Ntk_t representing an AIG, by skipping object ID number 0 reserved for the constant node.
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2014-06-30 15:21:47 -07:00 |
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Alan Mishchenko
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55404ca1af
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Changes and improvements to different packages.
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2014-06-28 14:31:01 -07:00 |
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Alan Mishchenko
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933b749676
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Changes and improvements to different packages.
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2014-06-28 14:25:38 -07:00 |
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Alan Mishchenko
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a68ec38df1
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Changes and improvements to different packages.
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2014-06-26 09:51:53 -07:00 |
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Alan Mishchenko
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2edf2a970e
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Improvements to power-aware mapping.
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2014-06-23 18:05:51 -07:00 |
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Alan Mishchenko
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f79d8e4b04
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Improvements to CNF generation.
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2014-06-23 14:50:46 -07:00 |
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Alan Mishchenko
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44d9c7e543
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Improvements to CNF generation.
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2014-06-23 13:11:59 -07:00 |
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Alan Mishchenko
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f93e524421
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Added command &mux_profile.
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2014-06-22 17:08:21 -07:00 |
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Alan Mishchenko
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13dd4eeb59
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Experiments with balancing.
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2014-06-22 00:50:07 -07:00 |
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Alan Mishchenko
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1e76ebdf3b
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New tools for profiling verification miters.
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2014-06-20 17:51:35 -07:00 |
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Alan Mishchenko
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f04d32732b
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Added quick GIG parser.
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2014-06-19 21:16:30 -07:00 |
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Alan Mishchenko
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f98f610bab
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Added delay-oriented balancing to unmapping in &st.
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2014-06-19 19:12:10 -07:00 |
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Alan Mishchenko
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85e23c8459
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Various changes to enable better CNF generation.
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2014-06-17 21:00:51 -07:00 |
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Alan Mishchenko
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a03a726de2
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Bug fix in writing latch init values in 'write_aiger'.
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2014-06-17 14:21:28 -07:00 |
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Alan Mishchenko
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dd867b404a
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Added transformation of CEX after 'fix_aig' and checking of transformed CEXes using 'testcex -a'.
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2014-06-17 12:21:48 -07:00 |
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Alan Mishchenko
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e20364896e
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Bug fix in CEC generation after rarity simulation and few small changes.
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2014-06-16 16:46:39 -07:00 |
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Alan Mishchenko
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2340d279bd
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Adding support of multi-output problems in &splitprove.
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2014-06-15 22:58:25 -07:00 |
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Alan Mishchenko
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e2637595f8
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Updates and bug fixes.
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2014-06-15 16:28:05 -07:00 |
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Alan Mishchenko
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cf993a9d90
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Adding more features to the synthesis script &syn2.
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2014-06-14 19:03:05 -07:00 |
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Alan Mishchenko
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0ac22c9e1d
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Specializing some truth-table functions to 6 inputs.
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2014-06-14 18:29:19 -07:00 |
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