Alan Mishchenko 47dde4e478 Correcting incorrect handling of timing in several &-commands.

2014-08-25 16:55:39 -07:00

..

abc

Added DSD-based collapsing &dsd.

2014-08-16 11:54:49 -07:00

abci

Correcting incorrect handling of timing in several &-commands.

2014-08-25 16:55:39 -07:00

cmd

Adding barrier buffers.

2014-03-16 21:56:28 -07:00

io

Improvements to power-aware mapping.

2014-06-23 18:05:51 -07:00

main

Cleanup and bug fixing in hierarchy handling.

2014-04-09 12:51:08 -07:00

test

Updating project settings to have simpler include paths.

2012-07-07 20:14:12 -07:00

ver

Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, such as [7:7], which seems to help in some cases.

2014-08-02 17:00:24 -07:00