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4,405 Commits 27 Branches 57 Tags 58 MiB
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134 Commits

Author SHA1 Message Date
Alan Mishchenko a2d59be3f7 Integrating SAT-based CEX minimization (bug fix). 2018-03-25 18:19:06 -07:00
Alan Mishchenko e639e8fd1b Integrating SAT-based CEX minimization. 2018-03-25 16:46:09 -07:00
Alan Mishchenko 1743979b75 Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes. 2017-12-03 14:39:11 -08:00
Alan Mishchenko 8bff9aa1cd Adding PDR with abstraction. 2017-02-10 17:36:20 -08:00
Alan Mishchenko f2d096c9f0 Improving CEX minimization. 2017-02-10 13:20:20 -08:00
Alan Mishchenko e21c7d72f3 Updates to arithmetic verification. 2017-01-30 08:39:26 -08:00
Alan Mishchenko b3514ee7e0 Commenting out bailout in 'print_cex' when CEX has latches initialized to 1. 2016-11-30 12:07:08 -08:00
Alan Mishchenko 76c4d22229 Parser for JSON format. 2016-10-25 17:17:37 -07:00
Alan Mishchenko 3c3a770a17 New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge). 2016-06-16 21:09:39 -07:00
Alan Mishchenko ada21a655f New multi-output PLA reader and preprocessor (read_plamo). 2016-06-16 15:22:03 -07:00
Alan Mishchenko a18da5c878 Detecting properties of internal nodes. 2016-06-12 19:07:46 -07:00
Alan Mishchenko ea7d10d45d Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset). 2016-05-12 13:59:30 -07:00
Alan Mishchenko 11f1a249ae Updating GIG parser. 2016-05-01 17:43:50 -07:00
Alan Mishchenko 2d6a6f6654 Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG (cubes -x; st). 2016-04-11 21:42:00 -07:00
Alan Mishchenko fb5d4a664d Adding switch '-b' in 'read_pla'. 2015-03-18 10:18:46 +07:00
Alan Mishchenko 68467cfff7 Fixed a typo in variable names. 2015-02-07 22:29:14 -08:00
Alan Mishchenko eb270018b9 Esperiments with MO PLA optimization. 2015-02-03 17:24:30 -08:00
Alan Mishchenko 6b6e5861e5 Integrating barrier buffers. 2014-12-13 20:45:11 -08:00
Alan Mishchenko 968be1577b Generation of barrier-buffers for hierarchical design. 2014-11-11 23:17:48 -08:00
Alan Mishchenko 5ebf135b6a Adding cyclicity check for netlist with boxes. 2014-11-10 14:55:27 -08:00
Alan Mishchenko 98e377bdff Adding features to CNF generation. 2014-09-28 12:10:13 -07:00
Alan Mishchenko dcb7d0d3fc New word-level representation package. 2014-09-12 13:40:48 -07:00
Alan Mishchenko 49f2ec22b9 Bug fix in transferring timing info. 2014-09-09 22:50:15 -07:00
Alan Mishchenko 2edf2a970e Improvements to power-aware mapping. 2014-06-23 18:05:51 -07:00
Alan Mishchenko f79d8e4b04 Improvements to CNF generation. 2014-06-23 14:50:46 -07:00
Alan Mishchenko 44d9c7e543 Improvements to CNF generation. 2014-06-23 13:11:59 -07:00
Alan Mishchenko f04d32732b Added quick GIG parser. 2014-06-19 21:16:30 -07:00
Baruch Sterin 26c92f161a add an option to write_cex to write the CEX in AIGER 1.9 format. 2014-05-12 15:20:17 -07:00
Alan Mishchenko 6095b15174 Added dumping original object names into a file. 2014-04-26 23:47:54 -07:00
Alan Mishchenko b94b810297 Renamed Abc_Lib_t into Abc_Des_t and removed some dead code. 2014-04-09 10:16:07 -07:00
Alan Mishchenko f6ae0e41f3 Better CEX minimization and renaming of write_counter into write_cex. 2014-04-04 13:14:16 -07:00
Alan Mishchenko 89eed1aaf9 Adding barrier buffers. 2014-03-16 21:56:28 -07:00
Alan Mishchenko c97a9c0d18 Changes to LUT mappers. 2014-03-09 20:21:09 -07:00
Alan Mishchenko 737e4671ce Adding check for the presence of precomputed data. 2013-12-29 14:39:25 +07:00
Alan Mishchenko 227963f03d New command &write_cnf. 2013-12-18 00:22:26 +07:00
Alan Mishchenko efa6b54b5e Debugging and finetuning the flow. 2013-09-17 21:47:39 -07:00
Alan Mishchenko 7d3976a763 Unifying standard cell library representations. 2013-09-17 13:16:20 -07:00
Alan Mishchenko d5234332fb New MFS package. 2013-05-24 22:35:22 -07:00
Alan Mishchenko db7852bba7 Improvements to LMS code. 2012-11-06 18:04:23 -08:00
Alan Mishchenko fac3976621 Adding binary file dumping for truth tables. 2012-10-25 13:55:04 -07:00
Alan Mishchenko 059da57476 Adding binary file dumping for truth tables. 2012-10-25 11:45:19 -07:00
Alan Mishchenko 7ecea8d40d Added hierarchical BLIF output for mapping with LUT structures (write_blif -a -S <XYZ>). 2012-10-24 21:12:50 -07:00
Alan Mishchenko d261e617fc Added command to transform GIA into the file with truth tables for each output. 2012-10-10 01:11:24 -07:00
Alan Mishchenko 71bdfae941 Replacing 'st_table' by 'st__table' to resolve linker problems. 2012-09-29 17:11:03 -04:00
Alan Mishchenko aed3b3a13a Cleaned up interfaces of genlib/liberty/supergate reading/writing. 2012-09-25 01:34:26 -07:00
Alan Mishchenko d0197d8378 Changed printouts in a few places in supergate computation. 2012-09-24 22:57:01 -07:00
Alan Mishchenko 5f09917c22 Added simplification before the concurrent call to PDR. 2012-09-20 19:51:39 -07:00
Alan Mishchenko 266af49386 Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 13:12:51 -07:00
Alan Mishchenko bc44087bac Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 12:41:59 -07:00
Alan Mishchenko f59de3decc Fixes to Verilog parser. 2012-09-20 11:29:37 -07:00