Opensource DDR3 Controller

controller ddr3 ddr3-controller ddr3-phy fpga memory-controller phy verilog

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Angelo Jacobo 6b9607563e added sby file for formal verif		2023-03-02 20:11:10 +08:00
rtl	added initial RTLs	2023-03-02 20:04:37 +08:00
LICENSE	Initial commit	2023-03-02 19:44:58 +08:00
README.md	Initial commit	2023-03-02 19:44:58 +08:00
ddr3_controller.sby	added sby file for formal verif	2023-03-02 20:11:10 +08:00
run.sh	added shell script for compiling RTL	2023-03-02 20:07:08 +08:00

README.md

DDR3_Controller