AngeloJacobo
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bc66655ca7
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just fixed delay
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2023-08-04 07:54:20 +08:00 |
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AngeloJacobo
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d2ae29c26a
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simulation file for SODIMM
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2023-07-24 17:34:40 +08:00 |
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AngeloJacobo
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4e5b98f485
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use SODIMM instead of DIMM in simulation
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2023-07-24 17:32:56 +08:00 |
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AngeloJacobo
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487b026f6c
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add test to wb2
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2023-07-19 18:50:23 +08:00 |
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AngeloJacobo
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4f857e08f4
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add files back after git rm -r cached .
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2023-07-16 08:46:16 +08:00 |
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AngeloJacobo
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4273a172f5
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add wishbone 2 interface
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2023-07-13 18:57:35 +08:00 |
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AngeloJacobo
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29ef663d87
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set parameter FLY_BY_DELAY for each instantiated ddr3, the delay value is retrieved from 8192Mb_ddr3_parameters.vh
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2023-07-13 18:55:57 +08:00 |
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AngeloJacobo
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6655959514
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set different fly_by_delays for each lanes
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2023-07-13 18:54:25 +08:00 |
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AngeloJacobo
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ecb4cb5b2c
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moved FLY_BY_DELAY to this module so multiple instantiated ddr3 can have different set FLY_BY_DELAY
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2023-07-13 18:52:43 +08:00 |
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AngeloJacobo
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a4d4e3a099
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change all to non-blocking
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2023-07-06 20:32:12 +08:00 |
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AngeloJacobo
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ab17b8012b
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add average rate in report
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2023-07-05 16:44:31 +08:00 |
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AngeloJacobo
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ba00cb9063
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changed to non-blocking simulation
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2023-06-29 12:59:57 +08:00 |
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AngeloJacobo
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4ecf119454
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add error injections and use aux to determine ack request type
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2023-06-24 07:56:05 +08:00 |
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AngeloJacobo
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d93cf9fb4e
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fixed delay for data mask as same delay as dq
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2023-06-22 19:53:37 +08:00 |
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AngeloJacobo
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1937d34565
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create test 1(sequential access to first,middle,last rows) and test 2(random access)
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2023-06-15 17:46:14 +08:00 |
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AngeloJacobo
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60c9d5ae85
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added command type to be displayed in ASCII, changed all to posedge
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2023-06-10 08:41:37 +08:00 |
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AngeloJacobo
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806b49ebd5
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changed folder name with underscore
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2023-06-08 14:05:35 +08:00 |