AngeloJacobo
|
22f6db696c
|
automatically generate CL and CWL value based on ddr3 clock period
|
2024-05-05 15:21:55 +08:00 |
|
AngeloJacobo
|
bb26b0ef4c
|
fixed BYTE_LANES
|
2024-05-05 14:03:51 +08:00 |
|
AngeloJacobo
|
81a6ab32f9
|
removed OPT parameters (no use), and add defines
|
2024-05-05 13:32:37 +08:00 |
|
Angelo Jacobo
|
e9633ddae7
|
fixed instantiation template
|
2024-05-05 13:27:51 +08:00 |
|
Angelo Jacobo
|
da8eaa5d91
|
make internal test shorter during sim
|
2024-04-21 13:06:19 +08:00 |
|
Angelo Jacobo
|
81865ea2f8
|
make controller not dependent on chip-select cs_n
|
2024-04-20 15:03:47 +08:00 |
|
Angelo Jacobo
|
25685e5769
|
make internal test shorter during simulation
|
2024-04-20 12:24:49 +08:00 |
|
Angelo Jacobo
|
be88286891
|
fixed rtoi error in vivado
|
2024-04-20 12:20:50 +08:00 |
|
Angelo Jacobo
|
d489b867d7
|
fixed rtoi error in vivado
|
2024-04-20 12:20:20 +08:00 |
|
Angelo Jacobo
|
31f02da699
|
fixed rtoi error from vivado and add more options for speedbin and capacity
|
2024-04-20 12:18:04 +08:00 |
|
Angelo Jacobo
|
eb5774d518
|
add more comments
|
2024-03-28 14:59:56 +08:00 |
|
Angelo Jacobo
|
b308e507d1
|
add more comments
|
2024-03-28 14:21:16 +08:00 |
|
Angelo Jacobo
|
117a6dbdec
|
add more comments
|
2024-03-28 14:19:00 +08:00 |
|
Angelo Jacobo
|
21a35d4c49
|
add more comments
|
2024-03-28 14:05:46 +08:00 |
|
Angelo Jacobo
|
94c801990e
|
add more comments
|
2024-03-27 20:03:12 +08:00 |
|
Angelo Jacobo
|
a0fb015059
|
add more comments
|
2024-03-27 18:59:53 +08:00 |
|
Angelo Jacobo
|
4e16cac338
|
add more comments
|
2024-03-26 07:43:51 +08:00 |
|
Angelo Jacobo
|
3bafed0015
|
add more comments
|
2024-03-25 21:21:01 +08:00 |
|
Angelo Jacobo
|
4f73cf0a7a
|
add more comments
|
2024-03-24 15:05:14 +08:00 |
|
Angelo Jacobo
|
775a9ad1fe
|
add more comments
|
2024-03-24 13:39:29 +08:00 |
|
Angelo Jacobo
|
4e557d795b
|
add more comments
|
2024-03-23 11:48:01 +08:00 |
|
Angelo Jacobo
|
2c560b65ba
|
add more comments
|
2024-03-23 11:05:00 +08:00 |
|
Angelo Jacobo
|
910a4d00a3
|
add more comments
|
2024-03-23 08:42:22 +08:00 |
|
Angelo Jacobo
|
22bd2f1118
|
add more comments
|
2024-03-22 19:50:14 +08:00 |
|
Angelo Jacobo
|
cf3bc8c629
|
added more comments
|
2024-03-22 18:30:51 +08:00 |
|
AngeloJacobo
|
9a88f5540c
|
fix displayed report
|
2023-11-26 13:21:15 +08:00 |
|
AngeloJacobo
|
efc194a633
|
add instantiation template
|
2023-11-18 13:35:38 +08:00 |
|
AngeloJacobo
|
292f94c530
|
make 2nd wishbone removable via cyc line
|
2023-11-18 13:34:27 +08:00 |
|
AngeloJacobo
|
c2fc70fb6c
|
changed to picosecond-based instead of nanoseconds
|
2023-11-14 14:14:16 +08:00 |
|
AngeloJacobo
|
29ec2d0714
|
changed to picosecond-based instead of nanoseconds
|
2023-11-14 14:13:41 +08:00 |
|
AngeloJacobo
|
c514d492f1
|
changed to picosecond-based instead of nanoseconds
|
2023-11-14 14:11:40 +08:00 |
|
AngeloJacobo
|
0cfd8243ab
|
remove all IODELAY_GROUP lines
|
2023-11-11 11:32:14 +08:00 |
|
AngeloJacobo
|
33ec101b79
|
resolve bug "Conflicting initialization values for \index"
|
2023-11-11 10:18:15 +08:00 |
|
AngeloJacobo
|
896d3f4f23
|
clean description,and added missing parameters
|
2023-11-09 13:49:41 +08:00 |
|
AngeloJacobo
|
20953ee65f
|
fixed bug when ODELAY is not supported, clean file header and description
|
2023-11-09 13:25:39 +08:00 |
|
AngeloJacobo
|
a80bacb718
|
add reset control from controller to phy
|
2023-09-15 19:59:39 +08:00 |
|
AngeloJacobo
|
922d185643
|
now passes internal test calibration on klusterboard
|
2023-09-15 19:58:36 +08:00 |
|
AngeloJacobo
|
8c5c5e30cc
|
now passes internal test calibration on klusterboard
|
2023-09-15 19:58:12 +08:00 |
|
AngeloJacobo
|
20db6352e2
|
added write read test after calibration
|
2023-09-08 17:15:34 +08:00 |
|
AngeloJacobo
|
de4fb994b4
|
add debug lines and update wb2 registers
|
2023-09-05 20:17:10 +08:00 |
|
AngeloJacobo
|
92c25f394f
|
add wire for cue when write leveling starts
|
2023-09-05 18:33:20 +08:00 |
|
AngeloJacobo
|
2ee7e35bc5
|
add dci reset and optional DCIEN IO buffers
|
2023-09-05 18:32:30 +08:00 |
|
AngeloJacobo
|
03a1da2ce7
|
add calibration when DQS toggles early than DQ
|
2023-09-05 18:31:10 +08:00 |
|
AngeloJacobo
|
8f3d673e3d
|
fixed bug when issue write calibration has to be repeated
|
2023-08-22 16:40:44 +08:00 |
|
AngeloJacobo
|
83b7b95af4
|
pass verilator warning
|
2023-08-20 12:32:51 +08:00 |
|
AngeloJacobo
|
e2653d5793
|
reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP
|
2023-08-20 11:09:38 +08:00 |
|
AngeloJacobo
|
9769a7cfaa
|
pass formal for 8-lane config and pass verilator linting
|
2023-08-20 11:07:22 +08:00 |
|
AngeloJacobo
|
36c93689e5
|
redo read/write calibration if data read is wrong
|
2023-08-17 11:27:23 +08:00 |
|
AngeloJacobo
|
f296d08c6b
|
add option for ODELAY_SUPPORTED=0 and added port for i_ddr3_clk_90
|
2023-08-15 19:37:28 +08:00 |
|
AngeloJacobo
|
411febc1a8
|
add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
|
2023-08-15 19:35:44 +08:00 |