AngeloJacobo
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0fbd2e7cbb
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add more comments how design works
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2024-05-05 16:00:09 +08:00 |
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AngeloJacobo
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e4716b6675
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removed OPT parameter
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2024-05-05 15:43:40 +08:00 |
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AngeloJacobo
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22f6db696c
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automatically generate CL and CWL value based on ddr3 clock period
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2024-05-05 15:21:55 +08:00 |
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AngeloJacobo
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bb26b0ef4c
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fixed BYTE_LANES
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2024-05-05 14:03:51 +08:00 |
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AngeloJacobo
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81a6ab32f9
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removed OPT parameters (no use), and add defines
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2024-05-05 13:32:37 +08:00 |
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Angelo Jacobo
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e9633ddae7
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fixed instantiation template
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2024-05-05 13:27:51 +08:00 |
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Angelo Jacobo
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4491ddaa18
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update waveform config
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2024-04-28 16:22:30 +08:00 |
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Angelo Jacobo
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f70180b7c7
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add calibration_state signal to monitor calibration
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2024-04-28 16:22:11 +08:00 |
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Angelo Jacobo
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a14afa4c4b
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zero all delays
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2024-04-28 16:21:07 +08:00 |
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Angelo Jacobo
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926e167376
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zero all delays
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2024-04-28 16:20:39 +08:00 |
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Angelo Jacobo
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c4242a9cae
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Merge pull request #2 from AngeloJacobo/dev
make vivado waveform config more organized
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2024-04-21 14:05:59 +08:00 |
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Angelo Jacobo
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d959ecf8d2
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make vivado waveform config more organized
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2024-04-21 13:47:37 +08:00 |
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Angelo Jacobo
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da8eaa5d91
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make internal test shorter during sim
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2024-04-21 13:06:19 +08:00 |
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Angelo Jacobo
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a354a8d4ef
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Merge pull request #1 from AngeloJacobo/dev
Dev branch pull request
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2024-04-20 15:18:30 +08:00 |
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Angelo Jacobo
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81865ea2f8
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make controller not dependent on chip-select cs_n
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2024-04-20 15:03:47 +08:00 |
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Angelo Jacobo
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d2f0fd046b
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correct clock periods to ps
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2024-04-20 12:26:39 +08:00 |
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Angelo Jacobo
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25685e5769
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make internal test shorter during simulation
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2024-04-20 12:24:49 +08:00 |
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Angelo Jacobo
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be88286891
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fixed rtoi error in vivado
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2024-04-20 12:20:50 +08:00 |
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Angelo Jacobo
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d489b867d7
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fixed rtoi error in vivado
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2024-04-20 12:20:20 +08:00 |
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Angelo Jacobo
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31f02da699
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fixed rtoi error from vivado and add more options for speedbin and capacity
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2024-04-20 12:18:04 +08:00 |
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Angelo Jacobo
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eb5774d518
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add more comments
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2024-03-28 14:59:56 +08:00 |
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Angelo Jacobo
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b308e507d1
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add more comments
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2024-03-28 14:21:16 +08:00 |
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Angelo Jacobo
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117a6dbdec
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add more comments
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2024-03-28 14:19:00 +08:00 |
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Angelo Jacobo
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21a35d4c49
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add more comments
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2024-03-28 14:05:46 +08:00 |
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Angelo Jacobo
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94c801990e
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add more comments
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2024-03-27 20:03:12 +08:00 |
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Angelo Jacobo
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a0fb015059
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add more comments
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2024-03-27 18:59:53 +08:00 |
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Angelo Jacobo
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4e16cac338
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add more comments
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2024-03-26 07:43:51 +08:00 |
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Angelo Jacobo
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3bafed0015
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add more comments
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2024-03-25 21:21:01 +08:00 |
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Angelo Jacobo
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4f73cf0a7a
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add more comments
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2024-03-24 15:05:14 +08:00 |
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Angelo Jacobo
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775a9ad1fe
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add more comments
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2024-03-24 13:39:29 +08:00 |
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Angelo Jacobo
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4e557d795b
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add more comments
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2024-03-23 11:48:01 +08:00 |
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Angelo Jacobo
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2c560b65ba
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add more comments
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2024-03-23 11:05:00 +08:00 |
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Angelo Jacobo
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910a4d00a3
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add more comments
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2024-03-23 08:42:22 +08:00 |
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Angelo Jacobo
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22bd2f1118
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add more comments
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2024-03-22 19:50:14 +08:00 |
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Angelo Jacobo
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cf3bc8c629
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added more comments
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2024-03-22 18:30:51 +08:00 |
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Angelo Jacobo
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666f98d6c1
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Update LICENSE to GPL 3.0
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2024-02-23 19:00:14 +08:00 |
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Angelo Jacobo
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3311775af9
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Update README.md
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2023-11-29 19:52:02 +08:00 |
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Angelo Jacobo
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2d5c6a9e02
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Update README.md
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2023-11-29 19:50:16 +08:00 |
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Angelo Jacobo
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c4b40229a0
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Update README.md
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2023-11-29 19:48:13 +08:00 |
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Angelo Jacobo
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234c1c417f
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Update README.md
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2023-11-29 19:43:39 +08:00 |
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Angelo Jacobo
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9e1d329617
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Update README.md
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2023-11-29 19:40:21 +08:00 |
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Angelo Jacobo
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b2c0cb86ac
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Update README.md
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2023-11-29 19:18:51 +08:00 |
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Angelo Jacobo
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a4e775a112
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Update README.md
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2023-11-29 19:17:06 +08:00 |
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Angelo Jacobo
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be08a478ac
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move user documentation to this README
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2023-11-29 18:23:19 +08:00 |
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AngeloJacobo
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a566ef1960
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fix clock periods
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2023-11-26 15:07:22 +08:00 |
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AngeloJacobo
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5b3aa21ccc
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renamed folder
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2023-11-26 14:32:40 +08:00 |
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AngeloJacobo
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2a926cfc91
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moved ARTY-S7 project files
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2023-11-26 14:04:15 +08:00 |
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AngeloJacobo
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8d20a6f4d0
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moved wcfg file inside testbench
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2023-11-26 13:53:43 +08:00 |
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AngeloJacobo
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ba98139c56
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changed the extension of all simulation files to systemverilog
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2023-11-26 13:53:02 +08:00 |
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AngeloJacobo
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dcb48b75d3
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changed the extension of all simulation files to systemverilog
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2023-11-26 13:51:30 +08:00 |