Angelo Jacobo
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aa68c22169
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turn off ECC test by default
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2024-09-01 09:04:45 +08:00 |
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AngeloJacobo
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fc963c3c23
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simulation and formal are now passing for all ECC types
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2024-07-28 17:36:37 +08:00 |
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AngeloJacobo
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f80d4ac21b
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simulation passing for ECC_ENABLE = 3
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2024-07-15 18:31:49 +08:00 |
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AngeloJacobo
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de85925681
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add support for ECC_ENABLE = 3
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2024-07-06 21:24:01 +08:00 |
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AngeloJacobo
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71b0383cda
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add support for other memory address mapping (row_bank_col = 0,1, or 2)
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2024-07-06 09:01:34 +08:00 |
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AngeloJacobo
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c81c51c9f4
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add support for ECC = 1 and 2, passing simulation and formal verification
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2024-06-29 19:36:01 +08:00 |
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AngeloJacobo
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7d93717b72
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add initial ECC, ECC_ENABLE = 2 working
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2024-06-17 16:25:06 +08:00 |
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AngeloJacobo
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8fb24dd180
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add copyright on headers
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2024-06-09 12:01:30 +08:00 |
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AngeloJacobo
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a1b15fb9d6
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elevate DIC and RTT_NOM as parameters
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2024-06-09 10:50:18 +08:00 |
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AngeloJacobo
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9c440d535f
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fix bug in write levelling with cntvalue > 15 (reaches 31), changed mark_debug for debugging
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2024-06-02 19:19:17 +08:00 |
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AngeloJacobo
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a6982da97d
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match dic and rtt_nom settings
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2024-05-26 20:53:00 +08:00 |
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AngeloJacobo
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eaa45f01d5
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fix error in formal verif
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2024-05-26 20:27:53 +08:00 |
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AngeloJacobo
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57aebc6eef
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fixed error in slot calculation
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2024-05-25 13:49:48 +08:00 |
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AngeloJacobo
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18283f4436
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clean verilator lint by making parameters integer (instead of being inferred as real)
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2024-05-24 22:43:34 +08:00 |
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AngeloJacobo
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88a913f8da
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clean verilator lint
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2024-05-24 21:51:20 +08:00 |
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AngeloJacobo
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237752fa3d
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clean printed details
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2024-05-06 17:11:04 +08:00 |
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AngeloJacobo
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1d1fd96893
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fixed bug when READ_SLOT and WRITE_SLOT is the same
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2024-05-05 21:15:02 +08:00 |
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AngeloJacobo
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22f6db696c
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automatically generate CL and CWL value based on ddr3 clock period
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2024-05-05 15:21:55 +08:00 |
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AngeloJacobo
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81a6ab32f9
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removed OPT parameters (no use), and add defines
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2024-05-05 13:32:37 +08:00 |
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Angelo Jacobo
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da8eaa5d91
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make internal test shorter during sim
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2024-04-21 13:06:19 +08:00 |
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Angelo Jacobo
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81865ea2f8
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make controller not dependent on chip-select cs_n
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2024-04-20 15:03:47 +08:00 |
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Angelo Jacobo
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25685e5769
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make internal test shorter during simulation
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2024-04-20 12:24:49 +08:00 |
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Angelo Jacobo
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31f02da699
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fixed rtoi error from vivado and add more options for speedbin and capacity
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2024-04-20 12:18:04 +08:00 |
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Angelo Jacobo
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eb5774d518
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add more comments
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2024-03-28 14:59:56 +08:00 |
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Angelo Jacobo
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b308e507d1
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add more comments
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2024-03-28 14:21:16 +08:00 |
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Angelo Jacobo
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117a6dbdec
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add more comments
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2024-03-28 14:19:00 +08:00 |
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Angelo Jacobo
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21a35d4c49
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add more comments
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2024-03-28 14:05:46 +08:00 |
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Angelo Jacobo
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94c801990e
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add more comments
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2024-03-27 20:03:12 +08:00 |
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Angelo Jacobo
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a0fb015059
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add more comments
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2024-03-27 18:59:53 +08:00 |
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Angelo Jacobo
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4e16cac338
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add more comments
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2024-03-26 07:43:51 +08:00 |
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Angelo Jacobo
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3bafed0015
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add more comments
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2024-03-25 21:21:01 +08:00 |
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Angelo Jacobo
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4f73cf0a7a
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add more comments
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2024-03-24 15:05:14 +08:00 |
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Angelo Jacobo
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775a9ad1fe
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add more comments
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2024-03-24 13:39:29 +08:00 |
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Angelo Jacobo
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4e557d795b
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add more comments
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2024-03-23 11:48:01 +08:00 |
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Angelo Jacobo
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2c560b65ba
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add more comments
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2024-03-23 11:05:00 +08:00 |
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Angelo Jacobo
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910a4d00a3
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add more comments
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2024-03-23 08:42:22 +08:00 |
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Angelo Jacobo
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22bd2f1118
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add more comments
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2024-03-22 19:50:14 +08:00 |
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Angelo Jacobo
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cf3bc8c629
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added more comments
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2024-03-22 18:30:51 +08:00 |
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AngeloJacobo
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9a88f5540c
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fix displayed report
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2023-11-26 13:21:15 +08:00 |
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AngeloJacobo
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292f94c530
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make 2nd wishbone removable via cyc line
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2023-11-18 13:34:27 +08:00 |
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AngeloJacobo
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c514d492f1
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changed to picosecond-based instead of nanoseconds
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2023-11-14 14:11:40 +08:00 |
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AngeloJacobo
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33ec101b79
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resolve bug "Conflicting initialization values for \index"
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2023-11-11 10:18:15 +08:00 |
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AngeloJacobo
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20953ee65f
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fixed bug when ODELAY is not supported, clean file header and description
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2023-11-09 13:25:39 +08:00 |
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AngeloJacobo
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8c5c5e30cc
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now passes internal test calibration on klusterboard
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2023-09-15 19:58:12 +08:00 |
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AngeloJacobo
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20db6352e2
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added write read test after calibration
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2023-09-08 17:15:34 +08:00 |
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AngeloJacobo
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de4fb994b4
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add debug lines and update wb2 registers
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2023-09-05 20:17:10 +08:00 |
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AngeloJacobo
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03a1da2ce7
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add calibration when DQS toggles early than DQ
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2023-09-05 18:31:10 +08:00 |
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AngeloJacobo
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8f3d673e3d
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fixed bug when issue write calibration has to be repeated
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2023-08-22 16:40:44 +08:00 |
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AngeloJacobo
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9769a7cfaa
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pass formal for 8-lane config and pass verilator linting
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2023-08-20 11:07:22 +08:00 |
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AngeloJacobo
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36c93689e5
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redo read/write calibration if data read is wrong
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2023-08-17 11:27:23 +08:00 |