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2023-04-27 20:02:37 +08:00
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2023-04-27 19:56:43 +08:00
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2023-04-27 19:48:59 +08:00
c0172c24a3
added read phy interface
2023-04-27 19:40:35 +08:00
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2023-04-20 22:20:44 +08:00
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2023-04-20 19:59:55 +08:00
a5b14accf4
added PHY interface
2023-04-20 19:37:15 +08:00
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2023-04-20 19:20:47 +08:00
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2023-04-06 19:56:55 +08:00
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2023-04-06 19:45:09 +08:00
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2023-04-06 19:44:30 +08:00
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2023-04-06 19:01:02 +08:00
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2023-04-06 17:54:16 +08:00
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2023-04-06 17:34:05 +08:00
1380c03c85
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2023-04-06 17:31:23 +08:00
ae201bfd04
removed irrelevant comments
2023-03-30 19:18:55 +08:00
192a9950e4
applied :retab
2023-03-30 18:27:58 +08:00
7e1a145238
added gtkwave template
2023-03-30 18:19:14 +08:00
fa5fcc2615
use a 4-bit counter plus a 4-bit mask for tracking delay in every bank
...
this is the optimized delay-tracking mechanism on which the 32-bit shift regs is replaced by a 4-bit counter plus a 4-bit mask. This uses lower resources but still able to track the delays and the exact slot number where the delay is already satisfied (hence no added latency)
2023-03-30 18:17:46 +08:00
fa3f5e0d65
use 32-bit shift reg for tracking delay inside every bank
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There are 4 delays being tracked (delay_before_precharge, delay_before_activate, delay_before_read, and delay_before_write) and 8 banks, that means 32x4x8 = 1024 bits needed for this tracking delay mechanism (totally wasteful!)
2023-03-30 18:14:09 +08:00
73e5f6b3de
added begin-end in short if-else statement
2023-03-23 20:35:37 +08:00
2018aa7ef7
changed license to Apache 2.0
2023-03-23 20:18:46 +08:00
97092cf869
added logic for refresh sequence and bank access
2023-03-23 20:17:12 +08:00
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2023-03-23 20:10:22 +08:00
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2023-03-13 14:40:46 +08:00
7282e2565d
removed parameter file "ddr3_parameters.vh"
2023-03-09 18:16:01 +08:00
adb21070d4
used :retab and fixed tab spacing
2023-03-09 18:14:58 +08:00
c5d387fa24
added reset sequence and formal assertions
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- completed (mostly) the reset sequence
- added formal assertions and cover statements for reset sequence logic
- moved all parameters to this file
- fixed port widths
- converted IO ports to ANSI
2023-03-09 18:06:53 +08:00
71df6f7515
moved all parameters to the main verilog file
2023-03-09 18:01:58 +08:00
86e01b060e
Update README.md
2023-03-02 20:32:12 +08:00
084a681644
include directory on iverilog command
2023-03-02 20:20:14 +08:00
3633613c47
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2023-03-02 20:12:28 +08:00
6b9607563e
added sby file for formal verif
2023-03-02 20:11:10 +08:00
0f6f52390c
added shell script for compiling RTL
2023-03-02 20:07:08 +08:00
38109d8297
added initial RTLs
2023-03-02 20:04:37 +08:00
23d946c51c
Initial commit
2023-03-02 19:44:58 +08:00
Angelo Jacobo