OpenSTA/verilog/Verilog.i

// OpenSTA, Static Timing Analyzer
// Copyright (c) 2025, Parallax Software, Inc.
// 
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// 
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// 
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
// 
// The origin of this software must not be misrepresented; you must not
// claim that you wrote the original software.
// 
// Altered source versions must be plainly marked as such, and must not be
// misrepresented as being the original software.
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// This notice may not be removed or altered from any source distribution.

%module verilog

%{
#include "VerilogWriter.hh"
#include "Sta.hh"
%}

%inline %{

bool
read_verilog_cmd(const char *filename)
{
  return Sta::sta()->readVerilog(filename);
}

void
write_verilog_cmd(const char *filename,
		  bool sort,
		  bool include_pwr_gnd,
		  CellSeq *remove_cells)
{
  // This does NOT want the SDC (cmd) network because it wants
  // to see the sta internal names.
  Network *network = Sta::sta()->network();
  writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network);
  delete remove_cells;
}

%} // inline