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verilog reader cleanups 

commit 1f29e7bd737c70e408d61cd6c55be567a97c2aec
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Dec 28 15:31:41 2024 -0800

    mv unconnected_net_name_  into VerilogReader

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 1824cc9609c6b3d44792ebfa19b550472ff1306d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Dec 28 14:45:22 2024 -0800

    verilog reader use std::string for filename

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8d1d4c6639c54efcae85c476d46734e50909854c
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Dec 28 13:49:59 2024 -0800

    attribute_stmts() -> attributeStmts()

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 7e6bb731a279c0827a43dd3f66ab5885aea73014
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Dec 28 13:47:15 2024 -0800

    Sta::readerilog

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-12-28 15:48:18 -08:00
parent 26fccd8e7f
commit adaf73cb3a
5 changed files with 40 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
include/sta/Sta.hh
View File

@ -112,6 +112,7 @@ public:
bool infer_latches);
bool setMinLibrary(const char *min_filename,
const char *max_filename);
bool readVerilog(const char *filename);
// Network readers call this to notify the Sta to delete any previously
// linked network.
void readNetlistBefore();

12
search/Sta.cc
View File

@ -723,6 +723,18 @@ Sta::setMinLibrary(const char *min_filename,
return false;
}
bool
Sta::readVerilog(const char *filename)
{
NetworkReader *network = networkReader();
if (network) {
readNetlistBefore();
return readVerilogFile(filename, network);
}
else
return false;
}
void
Sta::readNetlistBefore()
{

11
verilog/Verilog.i
View File

@ -32,14 +32,7 @@ using sta::readVerilogFile;
bool
read_verilog_cmd(const char *filename)
{
Sta *sta = Sta::sta();
NetworkReader *network = sta->networkReader();
if (network) {
sta->readNetlistBefore();
return readVerilogFile(filename, network);
}
else
return false;
return Sta::sta()->readVerilog(filename);
}
void
@ -54,9 +47,9 @@ write_verilog_cmd(const char *filename,
bool include_pwr_gnd,
CellSeq *remove_cells)
{
Sta *sta = Sta::sta();
// This does NOT want the SDC (cmd) network because it wants
// to see the sta internal names.
Sta *sta = Sta::sta();
Network *network = sta->network();
writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network);
delete remove_cells;

35
verilog/VerilogReader.cc
View File

@ -35,7 +35,7 @@ VerilogParse_parse();
namespace sta {
VerilogReader *verilog_reader;
static const char *unconnected_net_name = reinterpret_cast<const char*>(1);
const char *VerilogReader::unconnected_net_name_ = reinterpret_cast<const char*>(1);
static string
verilogBusBitName(const char *bus_name,
@ -156,12 +156,8 @@ VerilogReader::~VerilogReader()
void
VerilogReader::deleteModules()
{
StringSet filenames;
for (const auto [name, module] : module_map_) {
filenames.insert(module->filename());
for (const auto [name, module] : module_map_)
delete module;
}
deleteContents(&filenames);
module_map_.clear();
}
@ -187,7 +183,8 @@ void
VerilogReader::init(const char *filename)
{
// Statements point to verilog_filename, so copy it.
filename_ = stringCopy(filename);
filename_ = filename;
filenames_.push_back(filename);
line_ = 1;
library_ = network_->findLibrary("verilog");
@ -267,12 +264,11 @@ VerilogReader::makeModule(const char *module_vname,
VerilogModule *module = new VerilogModule(module_name.c_str(), ports, stmts,
attribute_stmts, filename_, line, this);
cell = network_->makeCell(library_, module_name.c_str(), false, filename_);
cell = network_->makeCell(library_, module_name.c_str(), false, filename_.c_str());
for (VerilogAttributeStmt *stmt : *attribute_stmts) {
for (VerilogAttributeEntry *entry : *stmt->attribute_sequence()) {
for (VerilogAttributeEntry *entry : *stmt->attribute_sequence())
network_->setAttribute(cell, entry->key(), entry->value());
}
}
module_map_[cell] = module;
@ -582,10 +578,10 @@ VerilogReader::makeModuleInst(const char *module_vname,
int pin_index = lport->pinIndex();
const char *prev_net_name = net_names[pin_index];
if (prev_net_name
&& prev_net_name !=unconnected_net_name)
&& prev_net_name != unconnected_net_name_)
// Repeated port reference.
stringDelete(prev_net_name);
net_names[pin_index]=(net_name == nullptr) ? unconnected_net_name : net_name;
net_names[pin_index]=(net_name == nullptr) ? unconnected_net_name_ : net_name;
delete vpin;
net_port_ref_scalar_net_count_--;
}
@ -841,7 +837,7 @@ VerilogModule::VerilogModule(const char *name,
VerilogNetSeq *ports,
VerilogStmtSeq *stmts,
VerilogAttributeStmtSeq *attribute_stmts,
const char *filename,
string &filename,
int line,
VerilogReader *reader) :
VerilogStmt(line),
@ -908,7 +904,7 @@ VerilogModule::parseDcl(VerilogDcl *dcl,
dcl_map_[net_name] = dcl;
else if (!dcl->direction()->isInternal()) {
string net_vname = reader->netVerilogName(net_name);
reader->warn(1395, filename_, dcl->line(),
reader->warn(1395, filename_.c_str(), dcl->line(),
"signal %s previously declared on line %d.",
net_vname.c_str(),
existing_dcl->line());
@ -937,7 +933,7 @@ VerilogModule::checkInstanceName(VerilogInst *inst,
replacement_name = stringPrint("%s_%d", inst_name, i++);
} while (inst_names.findKey(replacement_name));
string inst_vname = reader->instanceVerilogName(inst_name);
reader->warn(1396, filename_, inst->line(),
reader->warn(1396, filename_.c_str(), inst->line(),
"instance name %s duplicated - renamed to %s.",
inst_vname.c_str(),
replacement_name);
@ -1035,8 +1031,7 @@ VerilogLibertyInst::~VerilogLibertyInst()
int port_count = cell_->portBitCount();
for (int i = 0; i < port_count; i++) {
const char *net_name = net_names_[i];
if (net_name
&& net_name != unconnected_net_name)
if (net_name != VerilogReader::unconnected_net_name_)
stringDelete(net_name);
}
delete [] net_names_;
@ -1937,7 +1932,7 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
cell = network_->cell(lib_cell);
Instance *inst = network_->makeInstance(cell, mod_inst->instanceName(),
parent);
VerilogAttributeStmtSeq *attribute_stmts = mod_inst->attribute_stmts();
VerilogAttributeStmtSeq *attribute_stmts = mod_inst->attributeStmts();
for (VerilogAttributeStmt *stmt : *attribute_stmts) {
for (VerilogAttributeEntry *entry : *stmt->attribute_sequence()) {
network_->setAttribute(inst, entry->key(), entry->value());
@ -2129,7 +2124,7 @@ VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst,
Cell *cell = reinterpret_cast<Cell*>(lib_cell);
Instance *inst = network_->makeInstance(cell, lib_inst->instanceName(),
parent);
VerilogAttributeStmtSeq *attribute_stmts = lib_inst->attribute_stmts();
VerilogAttributeStmtSeq *attribute_stmts = lib_inst->attributeStmts();
for (VerilogAttributeStmt *stmt : *attribute_stmts) {
for (VerilogAttributeEntry *entry : *stmt->attribute_sequence()) {
network_->setAttribute(inst, entry->key(), entry->value());
@ -2144,7 +2139,7 @@ VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst,
if (net_name) {
Net *net = nullptr;
// If the pin is unconnected (ie, .A()) make the pin but not the net.
if (net_name != unconnected_net_name) {
if (net_name != unconnected_net_name_) {
VerilogDcl *dcl = parent_module->declaration(net_name);
// Check for single bit bus reference .A(BUS) -> .A(BUS[LSB]).
if (dcl && dcl->isBus()) {

17
verilog/VerilogReaderPvt.hh
View File

@ -33,6 +33,7 @@ VerilogParse_error(const char *msg);
namespace sta {
using std::string;
using std::vector;
using std::set;
class Debug;
@ -158,7 +159,7 @@ public:
bool make_black_boxes,
Report *report);
int line() const { return line_; }
const char *filename() const { return filename_; }
const char *filename() const { return filename_.c_str(); }
void incrLine();
Report *report() const { return report_; }
void error(int id,
@ -181,6 +182,7 @@ public:
instanceVerilogName(const char *inst_name);
string
netVerilogName(const char *net_name);
static const char *unconnected_net_name_;
protected:
void init(const char *filename);
@ -279,7 +281,8 @@ protected:
Debug *debug_;
NetworkReader *network_;
const char *filename_;
string filename_;
vector<string> filenames_;
int line_;
gzFile stream_;
@ -340,13 +343,13 @@ public:
VerilogNetSeq *ports,
VerilogStmtSeq *stmts,
VerilogAttributeStmtSeq *attribute_stmts,
const char *filename,
string &filename,
int line,
VerilogReader *reader);
virtual ~VerilogModule();
const char *name() { return name_; }
const char *filename() { return filename_; }
VerilogAttributeStmtSeq *attribute_stmts() { return attribute_stmts_; }
const char *filename() { return filename_.c_str(); }
VerilogAttributeStmtSeq *attributeStmts() { return attribute_stmts_; }
VerilogNetSeq *ports() { return ports_; }
VerilogDcl *declaration(const char *net_name);
VerilogStmtSeq *stmts() { return stmts_; }
@ -361,7 +364,7 @@ private:
VerilogReader *reader);
const char *name_;
const char *filename_;
string &filename_;
VerilogNetSeq *ports_;
VerilogStmtSeq *stmts_;
VerilogDclMap dcl_map_;
@ -461,7 +464,7 @@ public:
virtual ~VerilogInst();
virtual bool isInstance() const { return true; }
const char *instanceName() const { return inst_name_; }
VerilogAttributeStmtSeq *attribute_stmts() const { return attribute_stmts_; }
VerilogAttributeStmtSeq *attributeStmts() const { return attribute_stmts_; }
void setInstanceName(const char *inst_name);
private: