mrg b4ebbdd5df Require either device models or device library. Remove sky130 flag.		2020-10-23 14:07:26 -07:00
..
base	Remove split_wl	2020-10-12 17:27:20 -07:00
bitcells	Make conditional wl and bl for dummy rows/cols.	2020-10-15 13:56:37 -07:00
characterizer	Require either device models or device library. Remove sky130 flag.	2020-10-23 14:07:26 -07:00
custom	move sky130 specific stuff to tech module lib	2020-10-13 04:48:10 -07:00
datasheet	…
drc	PEP8 cleanup	2020-04-15 11:24:28 -07:00
example_configs	Add load/slew scale option to config files	2020-10-16 13:52:36 -07:00
gdsMill	Search all shapes for boundary rather than specify structure	2020-10-08 14:04:19 -07:00
modules	Add bitlines to dummy modules	2020-10-16 13:43:56 -07:00
pgates	Temp fix to use old device names during Calibre LVS.	2020-10-21 17:05:48 -07:00
riscv	single port progess	2020-09-14 18:11:38 -07:00
router	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
sram	Allow 16-way column mux	2020-10-06 16:27:02 -07:00
tests	Remove temp files	2020-10-08 10:35:27 -07:00
verify	Initial pex sram test.	2020-10-02 13:32:52 -07:00
Makefile	…
debug.py	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
gen_stimulus.py	Fixed errors in extra rows characterization	2020-03-22 20:54:49 +00:00
globals.py	Don't use single slew for nominal corner	2020-10-16 16:51:28 -07:00
openram.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
options.py	Add load/slew scale option to config files	2020-10-16 13:52:36 -07:00
run_profile.sh	…
sram_factory.py	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
view_profile.py	…