Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport

2018-09-25 20:00:25 -07:00

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base

Improve comments. Simplify function interface for channel route.

2018-09-11 15:53:12 -07:00

characterizer

Corrections to functional test that adds multiple cs_b signals per port

2018-09-21 09:59:44 -07:00

gdsMill

Add back LEF blockages. Remove "absolute" flags from GDS output

2018-09-05 09:28:43 -07:00

modules

Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport

2018-09-25 20:00:25 -07:00

pgates

Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode.

2018-09-13 16:53:24 -07:00

router

Add inflate blockages and remove pins from blockages.

2018-09-05 11:06:17 -07:00

tests

Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport

2018-09-25 20:00:25 -07:00

verify

Hard code flatten commands for the unique id precharge array

2018-09-13 15:15:41 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Merge branch 'dev' into multiport_characterization

2018-08-29 01:27:37 -07:00

example_config_scn3me_subm.py

Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done.

2018-09-10 19:33:59 -07:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Change default to scn4m

2018-09-13 15:26:03 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

options.py

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-09-18 18:56:15 -07:00

sram_1bank.py

Altering control logic for multiport. Netlist changes only.

2018-09-12 00:59:07 -07:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_4bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_base.py

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-09-18 18:56:15 -07:00

sram_config.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00