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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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f1560375fc95ec1981060ff89251cbd8a719554f
OpenRAM/compiler/characterizer
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Michael Timothy Grimes 934959952b Corrections to functional test that adds multiple cs_b signals per port
2018-09-21 09:59:44 -07:00
..
__init__.py
Adding functional test to characterizer and unit tests in both single and multiport
2018-09-20 15:04:59 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
functional.py
Corrections to functional test that adds multiple cs_b signals per port
2018-09-21 09:59:44 -07:00
lib.py
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
stimuli.py
Adding functional test to characterizer and unit tests in both single and multiport
2018-09-20 15:04:59 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
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