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Jesse Cirimelli-Low 5a6c78865d singleport bitcell array laying out
2023-08-21 19:24:06 -07:00
..
configs
Sky130 tests will use 1 spare row and col
2023-07-20 15:18:32 -07:00
golden
Added sky130 golden spice file
2023-07-20 15:20:15 -07:00
sp_files
Added sky130 golden spice file
2023-07-20 15:20:15 -07:00
00_code_format_check_test.py
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01_library_test.py
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03_contact_test.py
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03_path_test.py
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03_ptx_1finger_nmos_test.py
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03_ptx_1finger_pmos_test.py
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03_ptx_3finger_nmos_test.py
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03_ptx_3finger_pmos_test.py
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03_ptx_4finger_nmos_test.py
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03_ptx_4finger_pmos_test.py
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03_ptx_no_contacts_test.py
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03_wire_test.py
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04_and2_dec_test.py
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04_and3_dec_test.py
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04_and4_dec_test.py
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04_column_mux_1rw_1r_test.py
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04_column_mux_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
04_column_mux_test.py
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04_dff_buf_test.py
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04_dummy_pbitcell_1rw1r1w_test.py
Split pbitcell tests to fix factory.reset() bug.
2023-03-14 08:50:00 -07:00
04_dummy_pbitcell_1rw_test.py
Split pbitcell tests to fix factory.reset() bug.
2023-03-14 08:50:00 -07:00
04_pand2_test.py
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04_pand3_test.py
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04_pand4_test.py
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04_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
04_pbuf_dec_8x_test.py
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04_pbuf_test.py
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04_pdriver_test.py
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04_pinv_1x_beta_test.py
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04_pinv_1x_test.py
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04_pinv_2x_test.py
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04_pinv_10x_test.py
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04_pinv_100x_test.py
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04_pinv_dec_1x_test.py
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04_pinvbuf_test.py
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04_pnand2_test.py
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04_pnand3_test.py
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04_pnand4_test.py
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04_pnor2_test.py
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04_precharge_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
04_precharge_pbitcell_test.py
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2023-03-10 10:44:54 -08:00
04_precharge_test.py
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2023-01-28 22:56:27 -08:00
04_pwrite_driver_test.py
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04_replica_pbitcell_1rw1r1w_test.py
Split pbitcell tests to fix factory.reset() bug.
2023-03-14 08:50:00 -07:00
04_replica_pbitcell_1rw_test.py
Split pbitcell tests to fix factory.reset() bug.
2023-03-14 08:50:00 -07:00
04_wordline_driver_test.py
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2023-01-28 22:56:27 -08:00
05_bitcell_array_1rw_1r_test.py
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05_bitcell_array_test.py
singleport bitcell array laying out
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05_dummy_array_test.py
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05_pbitcell_array_test.py
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06_column_decoder_16row_test.py
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06_hierarchical_decoder_16row_1rw_1r_test.py
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06_hierarchical_decoder_16row_test.py
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06_hierarchical_decoder_17row_1rw_1r_test.py
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06_hierarchical_decoder_17row_test.py
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06_hierarchical_decoder_32row_1rw_1r_test.py
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06_hierarchical_decoder_32row_test.py
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06_hierarchical_decoder_64row_1rw_1r_test.py
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06_hierarchical_decoder_64row_test.py
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06_hierarchical_decoder_132row_1rw_1r_test.py
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06_hierarchical_decoder_132row_test.py
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06_hierarchical_decoder_512row_1rw_1r_test.py
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06_hierarchical_decoder_512row_test.py
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06_hierarchical_decoder_4096row_1rw_1r_test.py
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06_hierarchical_decoder_4096row_test.py
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06_hierarchical_decoder_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
06_hierarchical_predecode2x4_1rw_1r_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_1rw_1r_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_test.py
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06_hierarchical_predecode4x16_test.py
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06_rom_decoder_test.py
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2023-03-30 11:30:50 -07:00
07_column_mux_array_2mux_1rw_1r_test.py
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07_column_mux_array_2mux_test.py
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07_column_mux_array_4mux_1rw_1r_test.py
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07_column_mux_array_4mux_test.py
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07_column_mux_array_8mux_1rw_1r_test.py
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07_column_mux_array_8mux_test.py
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07_column_mux_array_16mux_1rw_1r_test.py
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07_column_mux_array_16mux_test.py
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2023-01-28 22:56:27 -08:00
07_column_mux_array_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
07_rom_column_mux_array_test.py
Change ROM test permissions to include x
2023-03-30 11:30:50 -07:00
08_precharge_array_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
08_precharge_array_test.py
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2023-01-28 22:56:27 -08:00
08_rom_decoder_buffer_array_test.py
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2023-03-30 11:30:50 -07:00
08_rom_precharge_array_test.py
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2023-03-30 11:30:50 -07:00
08_wordline_buffer_array_test.py
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2023-01-28 22:56:27 -08:00
08_wordline_driver_array_1rw_1r_test.py
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2023-01-28 22:56:27 -08:00
08_wordline_driver_array_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
08_wordline_driver_array_test.py
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2023-01-28 22:56:27 -08:00
09_sense_amp_array_1rw_1r_test.py
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2023-01-28 22:56:27 -08:00
09_sense_amp_array_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
09_sense_amp_array_spare_cols_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
09_sense_amp_array_test.py
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10_rom_wordline_driver_array_test.py
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2023-03-30 11:30:50 -07:00
10_write_driver_array_1rw_1r_test.py
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2023-01-28 22:56:27 -08:00
10_write_driver_array_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
10_write_driver_array_spare_cols_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
10_write_driver_array_test.py
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2023-01-28 22:56:27 -08:00
10_write_driver_array_wmask_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
10_write_driver_array_wmask_spare_cols_test.py
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10_write_driver_array_wmask_test.py
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10_write_mask_and_array_1rw_1r_test.py
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2023-01-28 22:56:27 -08:00
10_write_mask_and_array_pbitcell_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
10_write_mask_and_array_test.py
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11_dff_array_test.py
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11_dff_buf_array_test.py
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12_tri_gate_array_test.py
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13_delay_chain_test.py
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14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
14_capped_replica_bitcell_array_dummies_1rw_1r_test.py
standardize array tests
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14_capped_replica_bitcell_array_dummies_1rw_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_capped_replica_bitcell_array_leftrbl_1rw_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
14_capped_replica_bitcell_array_norbl_1rw_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_replica_bitcell_array_bothrbl_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
14_replica_bitcell_array_dummies_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
14_replica_bitcell_array_dummies_1rw_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_replica_bitcell_array_leftrbl_1rw_1r_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_replica_bitcell_array_leftrbl_1rw_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_replica_bitcell_array_norbl_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
14_replica_bitcell_array_norbl_1rw_test.py
standardize 14* test structure
2023-04-03 10:08:57 -07:00
14_replica_bitcell_array_rightrbl_1rw_1r_test.py
fix bug in right rbl dual port replica array test
2023-04-07 11:30:15 -07:00
14_replica_column_1rw_1r_test.py
Merge remote-tracking branch 'origin/dev' into no_rbl
2023-02-20 22:11:02 -08:00
14_replica_column_1rw_test.py
Merge remote-tracking branch 'origin/dev' into no_rbl
2023-02-20 22:11:02 -08:00
14_replica_pbitcell_1rw1r_array_test.py
Split pbitcell tests to fix factory.reset() bug.
2023-03-14 08:50:00 -07:00
14_replica_pbitcell_1rw_array_test.py
Split pbitcell tests to fix factory.reset() bug.
2023-03-14 08:50:00 -07:00
14_rom_array_test.py
Change ROM test permissions to include x
2023-03-30 11:30:50 -07:00
15_global_bitcell_array_norbl_1rw_1r_test.py
add no rbl tests to 15 global array tests
2023-04-10 10:38:52 -07:00
15_global_bitcell_array_norbl_1rw_test.py
add no rbl tests to 15 global array tests
2023-04-10 10:38:52 -07:00
15_global_bitcell_array_rbl_1rw_1r_test.py
add no rbl tests to 15 global array tests
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15_global_bitcell_array_rbl_1rw_test.py
add no rbl tests to 15 global array tests
2023-04-10 10:38:52 -07:00
15_local_bitcell_array_bothrbl_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
15_local_bitcell_array_dummies_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
15_local_bitcell_array_dummies_1rw_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
15_local_bitcell_array_leftrbl_1rw_1r_test.py
apply 14* standard to 15_local tests
2023-04-03 10:11:49 -07:00
15_local_bitcell_array_leftrbl_1rw_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
15_local_bitcell_array_norbl_1rw_1r_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
15_local_bitcell_array_norbl_1rw_test.py
standardize array tests
2023-03-22 18:56:52 -07:00
15_local_bitcell_array_rightrbl_1rw_1r_test.py
apply 14* standard to 15_local tests
2023-04-03 10:11:49 -07:00
16_control_logic_delay_multiport_test.py
fix typos and standardize multiport control logic tests
2023-06-07 16:04:54 -07:00
16_control_logic_delay_r_test.py
update copyright
2023-06-08 12:36:12 -07:00
16_control_logic_delay_rw_test.py
update copyright
2023-06-08 12:36:12 -07:00
16_control_logic_delay_w_test.py
update copyright
2023-06-08 12:36:12 -07:00
16_control_logic_multiport_test.py
fix typos and standardize multiport control logic tests
2023-06-07 16:04:54 -07:00
16_control_logic_r_test.py
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2023-01-28 22:56:27 -08:00
16_control_logic_rw_test.py
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2023-01-28 22:56:27 -08:00
16_control_logic_w_test.py
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2023-01-28 22:56:27 -08:00
16_rom_control_logic_test.py
Change ROM test permissions to include x
2023-03-30 11:30:50 -07:00
18_port_address_16rows_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_address_16rows_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_address_256rows_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_address_512rows_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_2mux_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_2mux_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_4mux_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_4mux_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_8mux_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_8mux_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_16mux_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_16mux_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_nomux_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_nomux_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_spare_cols_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_wmask_1rw_1r_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
18_port_data_wmask_test.py
add has_rbl=True arg to tests
2023-06-08 13:10:03 -07:00
19_multi_bank_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_pmulti_bank_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_psingle_bank_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_rom_bank_test.py
Simplify ROM test.
2023-03-30 11:30:50 -07:00
19_single_bank_1w_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_2mux_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_2mux_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_4mux_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_4mux_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_8mux_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_8mux_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_16mux_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_16mux_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_global_bitline_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_nomux_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_nomux_norbl_1rw_1r_test.py
make norbl bank test executable
2023-06-05 12:08:22 -07:00
19_single_bank_nomux_norbl_test.py
add a bank test with no rbl
2023-04-25 09:27:56 -07:00
19_single_bank_nomux_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_spare_cols_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_wmask_1rw_1r_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
19_single_bank_wmask_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
20_psram_1bank_2mux_1rw_1w_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_psram_1bank_2mux_1rw_1w_wmask_test.py
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2023-01-28 22:56:27 -08:00
20_psram_1bank_2mux_1w_1r_test.py
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2023-01-28 22:56:27 -08:00
20_psram_1bank_2mux_test.py
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2023-01-28 22:56:27 -08:00
20_psram_1bank_4mux_1rw_1r_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_2mux_1rw_1r_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_sram_1bank_2mux_1w_1r_spare_cols_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_2mux_1w_1r_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_sram_1bank_2mux_global_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_2mux_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_sram_1bank_2mux_wmask_spare_cols_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_2mux_wmask_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_4mux_1rw_1r_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_4mux_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_8mux_1rw_1r_test.py
Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)
2023-07-24 19:21:31 -07:00
20_sram_1bank_8mux_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_sram_1bank_16mux_1rw_1r_test.py
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2023-01-28 22:56:27 -08:00
20_sram_1bank_16mux_test.py
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2023-01-28 22:56:27 -08:00
20_sram_1bank_32b_1024_wmask_test.py
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2023-01-28 22:56:27 -08:00
20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
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2023-01-28 22:56:27 -08:00
20_sram_1bank_nomux_1rw_1r_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_sram_1bank_nomux_norbl_1rw_1r_test.py
add norbl whole sram test
2023-06-05 15:26:26 -07:00
20_sram_1bank_nomux_norbl_test.py
add single port bank test for norbl
2023-06-12 12:50:50 -07:00
20_sram_1bank_nomux_spare_cols_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
20_sram_1bank_nomux_test.py
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2023-01-28 22:56:27 -08:00
20_sram_1bank_nomux_wmask_sparecols_test.py
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2023-01-28 22:56:27 -08:00
20_sram_1bank_nomux_wmask_test.py
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2023-01-28 22:56:27 -08:00
20_sram_1bank_ring_test.py
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2023-01-28 22:56:27 -08:00
20_sram_2bank_test.py
Remove factory.reset from all unit tests as we no longer use regress.py.
2023-03-10 10:44:54 -08:00
21_hspice_delay_test.py
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2023-01-28 22:56:27 -08:00
21_hspice_setuphold_test.py
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2023-01-28 22:56:27 -08:00
21_model_delay_test.py
Update Xyce char tests
2023-02-17 19:15:14 -08:00
21_ngspice_delay_extra_rows_test.py
Fixed golden values for ngspice delay tests
2023-05-15 16:28:35 -07:00
21_ngspice_delay_global_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
21_ngspice_delay_test.py
Fixed golden values for ngspice delay tests
2023-05-15 16:28:35 -07:00
21_ngspice_setuphold_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
21_regression_delay_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
21_xyce_delay_test.py
Update Xyce char tests
2023-02-17 19:15:14 -08:00
21_xyce_setuphold_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
22_psram_1bank_2mux_func_test.py
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2023-01-28 22:56:27 -08:00
22_psram_1bank_4mux_func_test.py
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2023-01-28 22:56:27 -08:00
22_psram_1bank_8mux_func_test.py
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2023-01-28 22:56:27 -08:00
22_psram_1bank_nomux_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_2mux_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_2mux_global_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_2mux_sparecols_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_4mux_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_8mux_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_nomux_1rw_1r_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_nomux_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_nomux_sparecols_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_1bank_wmask_1rw_1r_func_test.py
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2023-01-28 22:56:27 -08:00
22_sram_wmask_func_test.py
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2023-01-28 22:56:27 -08:00
23_lib_sram_linear_regression_test.py
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2023-01-28 22:56:27 -08:00
23_lib_sram_model_corners_test.py
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2023-01-28 22:56:27 -08:00
23_lib_sram_model_test.py
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2023-01-28 22:56:27 -08:00
23_lib_sram_prune_test.py
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2023-01-28 22:56:27 -08:00
23_lib_sram_test.py
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2023-01-28 22:56:27 -08:00
24_lef_sram_test.py
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2023-01-28 22:56:27 -08:00
25_verilog_multibank_test.py
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2023-01-28 22:56:27 -08:00
25_verilog_sram_test.py
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2023-01-28 22:56:27 -08:00
26_hspice_pex_pinv_test.py
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2023-01-28 22:56:27 -08:00
26_ngspice_pex_pinv_test.py
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2023-01-28 22:56:27 -08:00
26_sram_pex_test.py
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2023-01-28 22:56:27 -08:00
30_openram_back_end_library_test.py
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2023-01-28 22:56:27 -08:00
30_openram_back_end_test.py
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2023-01-28 22:56:27 -08:00
30_openram_front_end_library_test.py
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2023-01-28 22:56:27 -08:00
30_openram_front_end_test.py
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2023-01-28 22:56:27 -08:00
30_openram_sram_char_test.py
Renamed char and func unit tests
2023-05-23 13:46:05 -07:00
30_openram_sram_func_test.py
Renamed char and func unit tests
2023-05-23 13:46:05 -07:00
50_riscv_1k_1rw1r_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_1k_1rw_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_1rw1r_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_1rw1r_phys_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_1rw_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_1rw_phys_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_2k_1rw1r_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_2k_1rw_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_4k_1rw1r_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_4k_1rw_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_8k_1rw1r_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_8k_1rw_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_512b_1rw1r_func_test.py
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2023-01-28 22:56:27 -08:00
50_riscv_512b_1rw_func_test.py
Update copyright year
2023-01-28 22:56:27 -08:00
Makefile
Merge branch 'dev' into char
2023-07-19 12:06:34 -07:00
sram_1rw_1r_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_wmask_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
testutils.py
Remove the hack used for unit tests running on docker
2023-03-10 16:35:22 -08:00