mirror of https://github.com/VLSIDA/OpenRAM.git
186 lines
6.6 KiB
Python
186 lines
6.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import drc
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from vector import vector
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from sram_factory import factory
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import debug
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from globals import OPTS
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import logical_effort
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class sense_amp_array(design.design):
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"""
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Array of sense amplifiers to read the bitlines through the column mux.
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Dynamically generated sense amp array for all bitlines.
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"""
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def __init__(self, name, word_size, words_per_row):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("words_per_row: {0}".format(words_per_row))
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self.word_size = word_size
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self.words_per_row = words_per_row
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self.row_size = self.word_size * self.words_per_row
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def get_bl_name(self):
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bl_name = "bl"
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return bl_name
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def get_br_name(self):
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br_name = "br"
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return br_name
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@property
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def data_name(self):
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return "data"
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@property
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def en_name(self):
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return "en"
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_sense_amp_array()
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def create_layout(self):
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self.height = self.amp.height
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if self.bitcell.width > self.amp.width:
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self.width = self.bitcell.width * self.word_size * self.words_per_row
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else:
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self.width = self.amp.width * self.word_size * self.words_per_row
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self.place_sense_amp_array()
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self.add_layout_pins()
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self.route_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(0, self.word_size):
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self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT")
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self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.en_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.amp = factory.create(module_type="sense_amp")
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self.add_mod(self.amp)
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# This is just used for measurements,
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# so don't add the module
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self.bitcell = factory.create(module_type="bitcell")
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def create_sense_amp_array(self):
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self.local_insts = []
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for i in range(0, self.word_size):
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name = "sa_d{0}".format(i)
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self.local_insts.append(self.add_inst(name=name,
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mod=self.amp))
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self.connect_inst([self.get_bl_name() + "_{0}".format(i),
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self.get_br_name() + "_{0}".format(i),
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self.data_name + "_{0}".format(i),
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self.en_name, "vdd", "gnd"])
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def place_sense_amp_array(self):
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from tech import cell_properties
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if self.bitcell.width > self.amp.width:
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amp_spacing = self.bitcell.width * self.words_per_row
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else:
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amp_spacing = self.amp.width * self.words_per_row
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for i in range(0, self.word_size):
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xoffset = amp_spacing * i
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# align the xoffset to the grid of bitcells. This way we
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# know when to do the mirroring.
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grid_x = int(xoffset / self.amp.width)
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if cell_properties.bitcell.mirror.y and grid_x % 2:
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mirror = "MY"
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xoffset = xoffset + self.amp.width
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else:
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mirror = ""
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amp_position = vector(xoffset, 0)
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self.local_insts[i].place(offset=amp_position, mirror=mirror)
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def add_layout_pins(self):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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gnd_pin = inst.get_pin("gnd")
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self.add_power_pin(name="gnd",
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loc=gnd_pin.center(),
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start_layer=gnd_pin.layer,
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vertical=True)
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vdd_pin = inst.get_pin("vdd")
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self.add_power_pin(name="vdd",
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loc=vdd_pin.center(),
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start_layer=vdd_pin.layer,
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vertical=True)
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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dout_pin = inst.get_pin(inst.mod.dout_name)
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer=br_pin.layer,
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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def route_rails(self):
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# add sclk rail across entire array
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sclk = self.amp.get_pin(self.amp.en_name)
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0, 1)
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self.add_layout_pin(text=self.en_name,
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layer=sclk.layer,
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offset=sclk_offset,
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width=self.width,
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height=drc("minwidth_" + sclk.layer))
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def input_load(self):
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return self.amp.input_load()
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def get_en_cin(self):
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"""Get the relative capacitance of all the sense amp enable connections in the array"""
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sense_amp_en_cin = self.amp.get_en_cin()
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return sense_amp_en_cin * self.word_size
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the PMOS isolation TX"""
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from tech import parameter
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# Bitcell drain load being used to estimate PMOS drain load
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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return drain_load
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