Jesse Cirimelli-Low d7c3bbea3e crba passing again norbl/leftrbl

2023-10-28 18:05:07 -07:00

..

__init__.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

sky130_bitcell_array.py

crba passing again norbl/leftrbl

2023-10-28 18:05:07 -07:00

sky130_bitcell_base_array.py

crba passing again norbl/leftrbl

2023-10-28 18:05:07 -07:00

sky130_bitcell.py

work on capped rba

2023-08-25 16:39:32 -07:00

sky130_capped_replica_bitcell_array.py

various refactor changes

2023-08-28 12:31:55 -07:00

sky130_col_cap_array.py

single port sky130 crba passing lvs

2023-08-30 20:59:02 -07:00

sky130_col_cap.py

Update copyright year

2023-01-28 22:56:27 -08:00

sky130_corner.py

placement working for sp capped rba, need fix rowcap patterns

2023-08-26 18:54:07 -07:00

sky130_dummy_array.py

both rbl replica array working

2023-09-11 11:23:39 -07:00

sky130_dummy_bitcell.py

Update copyright year

2023-01-28 22:56:27 -08:00

sky130_internal.py

Update copyright year

2023-01-28 22:56:27 -08:00

sky130_replica_bitcell_array.py

crba passing again norbl/leftrbl

2023-10-28 18:05:07 -07:00

sky130_replica_bitcell.py

Update copyright year

2023-01-28 22:56:27 -08:00

sky130_replica_column.py

crba passing again norbl/leftrbl

2023-10-28 18:05:07 -07:00

sky130_row_cap_array.py

crba passing again norbl/leftrbl

2023-10-28 18:05:07 -07:00

sky130_row_cap.py

Update copyright year

2023-01-28 22:56:27 -08:00