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OpenRAM/compiler/modules
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Eren Dogan 909ac6ce68 Add initial files for navigation router
2023-05-04 20:51:30 -07:00
..
__init__.py
Change rom_base_bank name and top pin names
2023-03-30 11:30:50 -07:00
and2_dec.py
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and3_dec.py
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and4_dec.py
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2023-01-28 22:56:27 -08:00
bank.py
use capped array to create banks
2023-02-21 09:58:46 -08:00
bitcell_1port.py
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2023-01-28 22:56:27 -08:00
bitcell_2port.py
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bitcell_array.py
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bitcell_base_array.py
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2023-01-28 22:56:27 -08:00
bitcell_base.py
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capped_replica_bitcell_array.py
update copyright
2023-02-21 14:04:31 -08:00
col_cap_array.py
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2023-01-28 22:56:27 -08:00
col_cap_bitcell_1port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
col_cap_bitcell_2port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
column_decoder.py
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2023-01-28 22:56:27 -08:00
column_mux_array.py
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column_mux.py
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control_logic_base.py
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control_logic.py
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delay_chain.py
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dff_array.py
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dff_buf_array.py
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dff_buf.py
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dff_inv_array.py
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dff_inv.py
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dff.py
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dummy_array.py
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dummy_bitcell_1port.py
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dummy_bitcell_2port.py
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dummy_pbitcell.py
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global_bitcell_array.py
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2023-01-28 22:56:27 -08:00
hierarchical_decoder.py
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hierarchical_predecode2x4.py
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hierarchical_predecode3x8.py
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hierarchical_predecode4x16.py
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hierarchical_predecode.py
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internal_base.py
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2023-01-28 22:56:27 -08:00
inv_dec.py
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2023-01-28 22:56:27 -08:00
local_bitcell_array.py
Merge remote-tracking branch 'origin/dev' into no_rbl
2023-02-20 22:11:02 -08:00
multibank.py
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2023-01-28 22:56:27 -08:00
nand2_dec.py
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nand3_dec.py
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2023-01-28 22:56:27 -08:00
nand4_dec.py
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2023-01-28 22:56:27 -08:00
orig_bitcell_array.py
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pand2.py
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pand3.py
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pand4.py
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2023-01-28 22:56:27 -08:00
pbitcell.py
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2023-01-28 22:56:27 -08:00
pbuf_dec.py
column control and address precharge
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pbuf.py
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pdriver.py
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2023-01-28 22:56:27 -08:00
pgate.py
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2023-01-28 22:56:27 -08:00
pinv_dec.py
Changes for test generation and simulation
2023-03-30 11:30:50 -07:00
pinv.py
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2023-01-28 22:56:27 -08:00
pinvbuf.py
revert changes to pinvbuf
2023-03-30 11:30:50 -07:00
pnand2.py
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2023-01-28 22:56:27 -08:00
pnand3.py
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pnand4.py
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pnor2.py
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2023-01-28 22:56:27 -08:00
port_address.py
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2023-01-28 22:56:27 -08:00
port_data.py
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2023-01-28 22:56:27 -08:00
precharge_array.py
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precharge.py
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2023-01-28 22:56:27 -08:00
ptristate_inv.py
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2023-01-28 22:56:27 -08:00
ptx.py
reoriented cell and added tap cell
2023-03-30 11:30:50 -07:00
pwrite_driver.py
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2023-01-28 22:56:27 -08:00
replica_bitcell_1port.py
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2023-01-28 22:56:27 -08:00
replica_bitcell_2port.py
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2023-01-28 22:56:27 -08:00
replica_bitcell_array.py
Merge remote-tracking branch 'origin/dev' into no_rbl
2023-02-20 22:11:02 -08:00
replica_column.py
Merge remote-tracking branch 'origin/dev' into no_rbl
2023-02-20 22:11:02 -08:00
replica_pbitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
rom_address_control_array.py
more top level routing cleanup
2023-03-30 11:30:50 -07:00
rom_address_control_buf.py
more code cleaning
2023-03-30 11:30:50 -07:00
rom_bank.py
a space
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rom_base_array.py
1kb rom DRC clean
2023-03-30 11:30:50 -07:00
rom_base_cell.py
precharge array test passing sky130
2023-03-30 11:30:50 -07:00
rom_column_mux_array.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_column_mux.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_control_logic.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_decoder.py
more code cleaning
2023-03-30 11:30:50 -07:00
rom_poly_tap.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_precharge_array.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_precharge_cell.py
precharge array test passing sky130
2023-03-30 11:30:50 -07:00
rom_wordline_driver_array.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
row_cap_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
row_cap_bitcell_1port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
row_cap_bitcell_2port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
sense_amp_array.py
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2023-01-28 22:56:27 -08:00
sense_amp.py
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2023-01-28 22:56:27 -08:00
sram_1bank.py
Add initial files for navigation router
2023-05-04 20:51:30 -07:00
sram_multibank_template.v
Shrunk address register in multibank verilog
2022-07-28 15:03:41 -07:00
sram_multibank.py
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2023-01-28 22:56:27 -08:00
template.py
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tri_gate_array.py
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tri_gate.py
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wordline_buffer_array.py
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2023-01-28 22:56:27 -08:00
wordline_driver_array.py
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2023-01-28 22:56:27 -08:00
wordline_driver.py
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2023-01-28 22:56:27 -08:00
write_driver_array.py
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2023-01-28 22:56:27 -08:00
write_driver.py
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2023-01-28 22:56:27 -08:00
write_mask_and_array.py
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2023-01-28 22:56:27 -08:00