Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 18:02:23 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
c479915c0232ae93d21139a092e59a7a3ce212db
OpenRAM/technology/sky130/modules
T
History
Jesse Cirimelli-Low 98fe4c74a4 colend fixes in progress
2022-06-15 22:34:21 -07:00
..
sky130_bitcell_array.py
Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
sky130_bitcell_base_array.py
colend fixes in progress
2022-06-15 22:34:21 -07:00
sky130_bitcell.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_col_cap_array.py
colend fixes in progress
2022-06-15 22:34:21 -07:00
sky130_col_cap.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_corner.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_dummy_array.py
colend fixes in progress
2022-06-15 22:34:21 -07:00
sky130_dummy_bitcell.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_internal.py
fix bitcell array opc errors
2021-12-14 22:15:27 -08:00
sky130_replica_bitcell_array.py
fix bl routing in rba
2022-05-19 21:45:48 -07:00
sky130_replica_bitcell.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_replica_column.py
colend fixes in progress
2022-06-15 22:34:21 -07:00
sky130_row_cap_array.py
remove add_mod in sky130
2021-12-22 15:51:49 -08:00
sky130_row_cap.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
Powered by Gitea Version: 1.27.2 Page: 1252ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API