OpenRAM/compiler/pgates
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
..
column_mux.py Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
pand2.py Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
pand3.py Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
pand4.py Add decoder4x16 2020-10-02 15:52:09 -07:00
pbuf.py Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
pbuf_dec.py Add pbuf_dec gate 2020-07-27 13:59:55 -07:00
pdriver.py Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
pgate.py Fix syntax errors in pgates for super edits 2020-08-12 11:15:32 -07:00
pinv.py Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
pinv_dec.py merge dev 2020-08-19 14:25:41 -07:00
pinvbuf.py Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
pnand2.py Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
pnand3.py Add pand4 and pnand4 2020-10-02 14:54:12 -07:00
pnand4.py Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
pnor2.py Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
precharge.py Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
ptristate_inv.py Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
ptx.py Merge branch 'super' into dev 2020-08-12 14:25:13 -07:00
pwrite_driver.py Fix syntax errors in pgates for super edits 2020-08-12 11:15:32 -07:00
wordline_driver.py Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00