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bank.py
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bank: Connect instances by their individual bl/br names
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2020-02-12 15:00:50 +01:00 |
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bank_select.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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bitcell_array.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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bitcell_base_array.py
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replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names
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2020-02-12 15:37:47 +01:00 |
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control_logic.py
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Changed layout input names of s_en AND gate to match the schematic
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2020-02-19 23:32:11 -08:00 |
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delay_chain.py
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…
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dff.py
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merge custom cell and module properties
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2020-02-12 04:09:40 +00:00 |
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dff_array.py
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add custom module file, make dff clk pin dynamic
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2020-02-04 23:35:06 -08:00 |
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dff_buf.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-02-12 06:54:03 +00:00 |
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dff_buf_array.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-02-12 06:54:03 +00:00 |
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dff_inv.py
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…
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dff_inv_array.py
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…
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dummy_array.py
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Fix base bitcell syntax error. Remove some unused imports.
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2020-01-30 01:58:30 +00:00 |
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hierarchical_decoder.py
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Nwell fixes in pgates.
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2020-02-06 16:20:09 +00:00 |
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hierarchical_predecode.py
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Nwell fixes in pgates.
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2020-02-06 16:20:09 +00:00 |
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hierarchical_predecode2x4.py
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…
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hierarchical_predecode3x8.py
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…
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module_type.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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multibank.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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port_address.py
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Add separate well design rules.
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2020-01-23 19:43:41 +00:00 |
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port_data.py
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port_data: Each submodule now specifies their bl/br names
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2020-02-12 15:00:50 +01:00 |
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precharge_array.py
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port_data: Each submodule now specifies their bl/br names
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2020-02-12 15:00:50 +01:00 |
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replica_bitcell_array.py
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replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names
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2020-02-12 15:37:47 +01:00 |
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replica_column.py
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Bitcell arrays: Allow mirroring on the y axis
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2020-01-28 15:51:21 +01:00 |
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sense_amp.py
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port_data: Each submodule now specifies their bl/br names
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2020-02-12 15:00:50 +01:00 |
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sense_amp_array.py
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port_data: Each submodule now specifies their bl/br names
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2020-02-12 15:00:50 +01:00 |
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single_level_column_mux_array.py
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port_data: Each submodule now specifies their bl/br names
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2020-02-12 15:00:50 +01:00 |
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tri_gate.py
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…
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tri_gate_array.py
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…
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wordline_driver.py
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Pgates are 8 M1 high by default. Port data is bitcell height.
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2020-01-30 03:34:04 +00:00 |
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write_driver.py
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port_data: Each submodule now specifies their bl/br names
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2020-02-12 15:00:50 +01:00 |
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write_driver_array.py
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port_data: Each submodule now specifies their bl/br names
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2020-02-12 15:00:50 +01:00 |
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write_mask_and_array.py
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Move write mask vias to center to avoid data pins.
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2019-12-20 11:48:27 -08:00 |
c1cb6bf512