OpenRAM/compiler
..
base
bitcells
characterizer
custom
datasheet
drc
example_configs
gdsMill
model_configs
modules
pgates
router
sram
tests
verify Initial klayout DRC/LVS options 2021-08-03 14:41:09 -07:00
Makefile
debug.py
gen_stimulus.py
globals.py
model_data_util.py
openram.py
options.py
printGDS.py
processGDS.py
run_profile.sh
sram_factory.py
uniquifyGDS.py
view_profile.py