mrg c1fedda575 Modifications for min area metal. ... Made add_via_stack_center iterative instead of recursive. Removed add_via_stack (non-center) since it isn't used. Add min area metal during iterative via insertion.		2020-06-30 15:07:34 -07:00
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pand2.py	Thin-cell decoder changes.	2020-05-29 10:36:07 -07:00
pand3.py	Vertical gates need both well contacts.	2020-05-13 16:54:35 -07:00
pbuf.py	Add no well option. Add stack gates vertical option.	2020-05-11 16:22:08 -07:00
pdriver.py	Thin-cell decoder changes.	2020-05-29 10:36:07 -07:00
pgate.py	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-06-25 08:57:37 -07:00
pinv.py	add missing parens	2020-06-25 08:02:08 -07:00
pinv_dec.py	move accuracy_requirement from techfile to config	2020-06-25 06:44:07 -07:00
pinvbuf.py	Fix pinvbuf layers	2020-06-09 17:16:35 -07:00
pnand2.py	use add_enclosure for npc contacts	2020-06-24 11:55:44 -07:00
pnand3.py	use add_enclosure for npc contacts	2020-06-24 11:55:44 -07:00
pnor2.py	use add_enclosure for npc contacts	2020-06-24 11:55:44 -07:00
precharge.py	Simplify precharge pin layer	2020-06-27 08:22:16 -07:00
ptristate_inv.py	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
ptx.py	Separate active and poly contact to gate rule	2020-06-24 09:17:39 -07:00
pwrite_driver.py	Modifications for min area metal.	2020-06-30 15:07:34 -07:00
single_level_column_mux.py	Add redundant implant for s8	2020-06-15 10:08:07 -07:00
wordline_driver.py	Change s8 to sky130	2020-06-12 14:23:26 -07:00