mirror of https://github.com/VLSIDA/OpenRAM.git
118 lines
4.2 KiB
Python
118 lines
4.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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from bitcell_base_array import bitcell_base_array
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from sram_factory import factory
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from globals import OPTS
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from tech import cell_properties
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class row_cap_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, cols, rows, column_offset=0, mirror=0, name=""):
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super().__init__(cols, rows, name, column_offset)
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self.mirror = mirror
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self.no_instances = True
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type="row_cap_{}".format(OPTS.bitcell))
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self.add_mod(self.dummy_cell)
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self.cell = factory.create(module_type="bitcell")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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for col in range(self.column_size):
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for row in range(1, self.row_size - 1):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.get_bitcell_pins(col, row))
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def get_bitcell_pins(self, col, row):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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pin_name = cell_properties.bitcell.cell_1rw1r.pin
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bitcell_pins = ["{0}_{1}".format(pin_name.wl0, row),
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"{0}_{1}".format(pin_name.wl1, row),
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"gnd"]
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return bitcell_pins
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def place_array(self, name_template, row_offset=0):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = self.cell.height
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(1, self.row_size - 1):
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.get_all_wl_names()
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for row in range(1, self.row_size - 1):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row + "_{0}".format(row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Add vdd/gnd via stacks
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for row in range(1, self.row_size - 1):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin.name,
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loc=pin.center(),
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start_layer=pin.layer)
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