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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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OpenRAM/compiler/pgates
T
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Michael Timothy Grimes af43fb6276 called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called
2018-08-15 02:19:36 -07:00
..
pbitcell.py
Remove carriage returns form python files
2018-08-07 09:44:01 -07:00
pgate.py
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
2018-03-23 08:14:09 -07:00
pinv.py
Line-wrap pinv debug formatting
2018-07-27 14:07:55 -07:00
pinvbuf.py
Make pinvbuf have unique names for GDS compliance.
2018-07-26 11:40:40 -07:00
pnand2.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
pnand3.py
called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called
2018-08-15 02:19:36 -07:00
pnor2.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
precharge.py
editted naming convention on precharge to accommodate multiport
2018-08-15 02:14:45 -07:00
ptx.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
single_level_column_mux.py
Add enclosing well to column mux. Move well contact to cell boundary.
2018-06-29 11:35:29 -07:00
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