Matt Guthaus 95a8688506 Rewrite blockage routines in router. Clean up GdsMill code.

2018-08-28 10:43:45 -07:00

..

bank_select.py

changed control signal names in bank select to accommodate multi-port changes in bank

2018-08-19 00:00:42 -07:00

bank.py

Finalized separation of netlist/layout creation.

2018-08-27 14:18:32 -07:00

bitcell_array.py

Add place_inst routine.

2018-08-27 10:42:40 -07:00

bitcell.py

Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly.

2018-08-26 14:37:17 -07:00

control_logic.py

Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port

2018-08-18 16:51:21 -07:00

delay_chain.py

Rewrite blockage routines in router. Clean up GdsMill code.

2018-08-28 10:43:45 -07:00

dff_array.py

Add place_inst routine.

2018-08-27 10:42:40 -07:00

dff_buf_array.py

Add place_inst routine.

2018-08-27 10:42:40 -07:00

dff_buf.py

Limit sizes for dff_buf too. Add comments about restriction.

2018-07-27 08:17:50 -07:00

dff_inv_array.py

Fix routing clk connections of dff arrays

2018-07-18 11:38:58 -07:00

dff_inv.py

Limit sizes for dff_buf too. Add comments about restriction.

2018-07-27 08:17:50 -07:00

dff.py

Add dff_buf for buffered flop arrays.

2018-03-04 16:13:10 -08:00

hierarchical_decoder.py

Finalized separation of netlist/layout creation.

2018-08-27 14:18:32 -07:00

hierarchical_predecode2x4.py

Add place_inst routine.

2018-08-27 10:42:40 -07:00

hierarchical_predecode3x8.py

Finalized separation of netlist/layout creation.

2018-08-27 14:18:32 -07:00

hierarchical_predecode.py

Finalized separation of netlist/layout creation.

2018-08-27 14:18:32 -07:00

ms_flop_array.py

Separate netlist/layout for flop and precharge array.

2018-08-27 10:54:21 -07:00

ms_flop.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

multibank.py

Initial refactor of signal and supply router classes.

2018-08-28 10:43:44 -07:00

precharge_array.py

Separate netlist/layout for flop and precharge array.

2018-08-27 10:54:21 -07:00

replica_bitcell.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

replica_bitline.py

Rewrite blockage routines in router. Clean up GdsMill code.

2018-08-28 10:43:45 -07:00

sense_amp_array.py

All modules have split netlist/layout.

2018-08-27 11:13:34 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

All modules have split netlist/layout.

2018-08-27 11:13:34 -07:00

tri_gate_array.py

All modules have split netlist/layout.

2018-08-27 11:13:34 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

All modules have split netlist/layout.

2018-08-27 11:13:34 -07:00

write_driver_array.py

All modules have split netlist/layout.

2018-08-27 11:13:34 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00